[Mesa-dev] [PATCH v4 3/4] i965: Fixed the CopyImageSubData for ETC2 on Gen < 8
Eleni Maria Stea
estea at igalia.com
Sun Feb 10 21:31:06 UTC 2019
For CopyImageSubData to copy the data during the 1st draw call, we need
to update the shadow tree right before the rendering.
v2:
- Added assertion that the miptree doesn't need update at the time we
update the texture surface. (Nanley Chery)
v3:
- As we now update the tree before the rendering we don't need to copy
the data during the unmap anymore. Removed the unnecessary update from
the intel_miptree_unmap in intel_mipmap_tree.c and modified the
intel_miptree_update_etc_shadow.* functions in the same file to update
properly the mipmap levels for the mipmaps generation to continue to
work after the change. (Nanley Chery)
---
src/mesa/drivers/dri/i965/brw_draw.c | 5 +++++
.../drivers/dri/i965/brw_wm_surface_state.c | 2 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 ++---------------
3 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index ec4fe0b096f..d00e0a726b1 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -559,6 +559,11 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
intel_update_r8stencil(brw, tex_obj->mt);
}
+
+ if (intel_miptree_has_etc_shadow(brw, tex_obj->mt) &&
+ tex_obj->mt->shadow_needs_update) {
+ intel_miptree_update_etc_shadow_levels(brw, tex_obj->mt);
+ }
}
/* Resolve color for each active shader image. */
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c2cf34aee71..437c7c82555 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -582,7 +582,7 @@ static void brw_update_texture_surface(struct gl_context *ctx,
mt = mt->shadow_mt;
format = ISL_FORMAT_R8_UINT;
} else if (intel_miptree_needs_fake_etc(brw, mt)) {
- assert(mt->shadow_mt);
+ assert(mt->shadow_mt && !mt->shadow_needs_update);
mt = mt->shadow_mt;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e50db649a23..86085db6a90 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3780,7 +3780,6 @@ intel_miptree_unmap(struct brw_context *brw,
unsigned int slice)
{
struct intel_miptree_map *map = mt->level[level].slice[slice].map;
- int level_w, level_h;
assert(mt->surf.samples == 1);
@@ -3790,20 +3789,10 @@ intel_miptree_unmap(struct brw_context *brw,
DBG("%s: mt %p (%s) level %d slice %d\n", __func__,
mt, _mesa_get_format_name(mt->format), level, slice);
- level_w = minify(mt->surf.phys_level0_sa.width,
- level - mt->first_level);
- level_h = minify(mt->surf.phys_level0_sa.height,
- level - mt->first_level);
-
if (map->unmap)
map->unmap(brw, mt, map, level, slice);
intel_miptree_release_map(mt, level, slice);
-
- if (intel_miptree_has_etc_shadow(brw, mt) && mt->shadow_needs_update) {
- intel_miptree_update_etc_shadow(brw, mt, level, slice, level_w,
- level_h);
- }
}
enum isl_surf_dim
@@ -3936,7 +3925,6 @@ intel_miptree_update_etc_shadow(struct brw_context *brw,
if (!mt->shadow_needs_update)
return;
- mt->shadow_needs_update = false;
smt = mt->shadow_mt;
etc_mode = GL_MAP_READ_BIT;
@@ -3989,10 +3977,9 @@ intel_miptree_update_etc_shadow_levels(struct brw_context *brw,
}
level_w = minify(smt->surf.logical_level0_px.width,
- level - smt->first_level);
+ level - smt->first_level + 1);
level_h = minify(smt->surf.logical_level0_px.height,
- level - smt->first_level);
+ level - smt->first_level + 1);
}
-
mt->shadow_needs_update = false;
}
--
2.20.1
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