[Mesa-dev] [PATCH v4 00/40] intel: VK_KHR_shader_float16_int8 implementation

Sat Feb 16 15:59:42 UTC 2019

I believe I've now reviewed everything except some of the validator patches
and the is_partial_write() patch.  The validator patches I'm hoping Matt or
Curro can look at.  For the is_partial_write() patch, I just need to
convince myself that it doesn't make the compiler significantly more bogus
than it already is today.

On Tue, Feb 12, 2019 at 5:57 AM Iago Toral Quiroga <itoral at igalia.com>
wrote:

> The changes in this version address review feedback to v3. The most
> significant
> changes include:
>
> 1. A more generic constant combining pass that can handle more
> constant types (not just F and HF) requested by Jason.
>
> 2. The addition of assembly validation for half-float restrictions, and
> also
> for mixed float mode, requested by Curro. It should be noted that this
> implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode
> float
> instructions at this moment so I have not empirically validated the
> restictions
> implemented here.
>
> As always, a branch with these patches is available for testing in the
> itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
> https://github.com/Igalia/mesa.
>
> Iago Toral Quiroga (40):
>   compiler/nir: add an is_conversion field to nir_op_info
>   intel/compiler: add a NIR pass to lower conversions
>   intel/compiler: split float to 64-bit opcodes from int to 64-bit
>   intel/compiler: handle b2i/b2f with other integer conversion opcodes
>   intel/compiler: assert restrictions on conversions to half-float
>   intel/compiler: lower some 16-bit float operations to 32-bit
>   intel/compiler: handle extended math restrictions for half-float
>   intel/compiler: implement 16-bit fsign
>   intel/compiler: drop unnecessary temporary from 32-bit fsign
>     implementation
>   compiler/nir: add lowering option for 16-bit fmod
>   compiler/nir: add lowering for 16-bit flrp
>   compiler/nir: add lowering for 16-bit ldexp
>   intel/compiler: add instruction setters for Src1Type and Src2Type.
>   intel/compiler: add new half-float register type for 3-src
>     instructions
>   intel/compiler: don't compact 3-src instructions with Src1Type or
>     Src2Type bits
>   intel/compiler: allow half-float on 3-source instructions since gen8
>   intel/compiler: set correct precision fields for 3-source float
>     instructions
>   intel/compiler: fix ddx and ddy for 16-bit float
>   intel/compiler: fix ddy for half-float in Broadwell
>   intel/compiler: workaround for SIMD8 half-float MAD in gen8
>   intel/compiler: split is_partial_write() into two variants
>   intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
>   intel/compiler: rework conversion opcodes
>   intel/compiler: implement isign for int8
>   intel/compiler: ask for an integer type if requesting an 8-bit type
>   intel/eu: force stride of 2 on NULL register for Byte instructions
>   intel/compiler: generalize the combine constants pass
>   intel/compiler: implement is_zero, is_one, is_negative_one for
>     8-bit/16-bit
>   intel/compiler: add a brw_reg_type_is_integer helper
>   intel/compiler: fix cmod propagation for non 32-bit types
>   intel/compiler: remove inexact algebraic optimizations from the
>     backend
>   intel/compiler: skip MAD algebraic optimization for half-float or
>     mixed mode
>   intel/compiler: also set F execution type for mixed float mode in BDW
>   intel/compiler: validate region restrictions for half-float
>     conversions
>   intel/compiler: validate conversions between 64-bit and 8-bit types
>   intel/compiler: skip validating restrictions on operand types for
>     mixed float
>   intel/compiler: validate region restrictions for mixed float mode
>   compiler/spirv: move the check for Int8 capability
>   anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
>   anv/device: expose VK_KHR_shader_float16_int8 in gen8+
>
>  src/compiler/nir/nir.h                        |   5 +
>  src/compiler/nir/nir_opcodes.py               |  73 +-
>  src/compiler/nir/nir_opcodes_c.py             |   1 +
>  src/compiler/nir/nir_opt_algebraic.py         |  11 +-
>  src/compiler/shader_info.h                    |   1 +
>  src/compiler/spirv/spirv_to_nir.c             |  11 +-
>  src/intel/Makefile.sources                    |   1 +
>  src/intel/compiler/brw_compiler.c             |   2 +
>  src/intel/compiler/brw_eu_compact.c           |   5 +-
>  src/intel/compiler/brw_eu_emit.c              |  36 +-
>  src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
>  src/intel/compiler/brw_fs.cpp                 | 101 ++-
>  .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
>  .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
>  .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
>  src/intel/compiler/brw_fs_cse.cpp             |   3 +-
>  .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
>  src/intel/compiler/brw_fs_generator.cpp       |  54 +-
>  src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
>  src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
>  src/intel/compiler/brw_fs_nir.cpp             |  87 +-
>  src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
>  .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
>  .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
>  src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
>  src/intel/compiler/brw_inst.h                 |   2 +
>  src/intel/compiler/brw_ir_fs.h                |   3 +-
>  src/intel/compiler/brw_nir.c                  |  22 +-
>  src/intel/compiler/brw_nir.h                  |   2 +
>  .../compiler/brw_nir_lower_conversions.c      | 158 ++++
>  src/intel/compiler/brw_reg_type.c             |   4 +
>  src/intel/compiler/brw_reg_type.h             |  18 +
>  src/intel/compiler/brw_shader.cpp             |  26 +
>  src/intel/compiler/meson.build                |   1 +
>  src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
>  src/intel/vulkan/anv_device.c                 |   9 +
>  src/intel/vulkan/anv_extensions.py            |   1 +
>  src/intel/vulkan/anv_pipeline.c               |   2 +
>  38 files changed, 1907 insertions(+), 216 deletions(-)
>  create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
>
> --
> 2.17.1
>
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