[Mesa-dev] [PATCH 5/6] radeonsi: compile clear and copy buffer compute shaders on demand

[Timothy Arceri]

Hi Guys,

Can we get this one into the next 18.3 release. It fixes a hang with 
Counter Strike on start-up. I'm a little concerned this just works 
around the problem but the patch seems safe for stable.

Thanks,
Tim

On 12/1/19 10:53 am, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> same as all other shaders
> ---
>   src/gallium/drivers/radeonsi/si_compute_blit.c | 14 ++++++++++++++
>   src/gallium/drivers/radeonsi/si_pipe.c         |  8 --------
>   2 files changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c
> index 11da04bed85..dfa77a98804 100644
> --- a/src/gallium/drivers/radeonsi/si_compute_blit.c
> +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
> @@ -104,36 +104,50 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx,
>   	info.block[2] = 1;
>   	info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave);
>   	info.grid[1] = 1;
>   	info.grid[2] = 1;
>   
>   	struct pipe_shader_buffer sb[2] = {};
>   	sb[0].buffer = dst;
>   	sb[0].buffer_offset = dst_offset;
>   	sb[0].buffer_size = size;
>   
> +	bool shader_dst_stream_policy = SI_COMPUTE_DST_CACHE_POLICY != L2_LRU;
> +
>   	if (src) {
>   		sb[1].buffer = src;
>   		sb[1].buffer_offset = src_offset;
>   		sb[1].buffer_size = size;
>   
>   		ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 2, sb);
> +
> +		if (!sctx->cs_copy_buffer) {
> +			sctx->cs_copy_buffer = si_create_dma_compute_shader(&sctx->b,
> +							     SI_COMPUTE_COPY_DW_PER_THREAD,
> +							     shader_dst_stream_policy, true);
> +		}
>   		ctx->bind_compute_state(ctx, sctx->cs_copy_buffer);
>   	} else {
>   		assert(clear_value_size >= 4 &&
>   		       clear_value_size <= 16 &&
>   		       util_is_power_of_two_or_zero(clear_value_size));
>   
>   		for (unsigned i = 0; i < 4; i++)
>   			sctx->cs_user_data[i] = clear_value[i % (clear_value_size / 4)];
>   
>   		ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, sb);
> +
> +		if (!sctx->cs_clear_buffer) {
> +			sctx->cs_clear_buffer = si_create_dma_compute_shader(&sctx->b,
> +							     SI_COMPUTE_CLEAR_DW_PER_THREAD,
> +							     shader_dst_stream_policy, false);
> +		}
>   		ctx->bind_compute_state(ctx, sctx->cs_clear_buffer);
>   	}
>   
>   	ctx->launch_grid(ctx, &info);
>   
>   	enum si_cache_policy cache_policy = get_cache_policy(sctx, coher, size);
>   	sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
>   		       (cache_policy == L2_BYPASS ? SI_CONTEXT_WRITEBACK_GLOBAL_L2 : 0);
>   
>   	if (cache_policy != L2_BYPASS)
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 92ce1e0699c..6b89a1192d9 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -503,28 +503,20 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
>   	si_init_viewport_functions(sctx);
>   
>   	if (sctx->chip_class >= CIK)
>   		cik_init_sdma_functions(sctx);
>   	else
>   		si_init_dma_functions(sctx);
>   
>   	if (sscreen->debug_flags & DBG(FORCE_DMA))
>   		sctx->b.resource_copy_region = sctx->dma_copy;
>   
> -	bool dst_stream_policy = SI_COMPUTE_DST_CACHE_POLICY != L2_LRU;
> -	sctx->cs_clear_buffer = si_create_dma_compute_shader(&sctx->b,
> -					     SI_COMPUTE_CLEAR_DW_PER_THREAD,
> -					     dst_stream_policy, false);
> -	sctx->cs_copy_buffer = si_create_dma_compute_shader(&sctx->b,
> -					     SI_COMPUTE_COPY_DW_PER_THREAD,
> -					     dst_stream_policy, true);
> -
>   	sctx->blitter = util_blitter_create(&sctx->b);
>   	if (sctx->blitter == NULL)
>   		goto fail;
>   	sctx->blitter->skip_viewport_restore = true;
>   
>   	si_init_draw_functions(sctx);
>   
>   	sctx->sample_mask = 0xffff;
>   
>   	if (sctx->chip_class >= GFX9) {
>