[Mesa-dev] [PATCH 2/5] radeonsi: add ability to bind images as image buffers
Marek Olšák
maraeo at gmail.com
Thu Feb 28 21:20:22 UTC 2019
From: Marek Olšák <marek.olsak at amd.com>
so that we can bind DCC (texture) as an image buffer.
---
src/gallium/drivers/radeonsi/si_descriptors.c | 9 ++++++---
src/gallium/drivers/radeonsi/si_pipe.h | 2 ++
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 0f22c55723c..ce67bdb87c8 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -662,38 +662,40 @@ si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
images->enabled_mask &= ~(1u << slot);
ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
}
}
static void
si_mark_image_range_valid(const struct pipe_image_view *view)
{
struct si_resource *res = si_resource(view->resource);
- assert(res && res->b.b.target == PIPE_BUFFER);
+ if (res->b.b.target != PIPE_BUFFER)
+ return;
util_range_add(&res->valid_buffer_range,
view->u.buf.offset,
view->u.buf.offset + view->u.buf.size);
}
static void si_set_shader_image_desc(struct si_context *ctx,
const struct pipe_image_view *view,
bool skip_decompress,
uint32_t *desc, uint32_t *fmask_desc)
{
struct si_screen *screen = ctx->screen;
struct si_resource *res;
res = si_resource(view->resource);
- if (res->b.b.target == PIPE_BUFFER) {
+ if (res->b.b.target == PIPE_BUFFER ||
+ view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
si_mark_image_range_valid(view);
si_make_buffer_descriptor(screen, res,
view->format,
view->u.buf.offset,
view->u.buf.size, desc);
si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
} else {
static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
@@ -780,21 +782,22 @@ static void si_set_shader_image(struct si_context *ctx,
return;
}
res = si_resource(view->resource);
if (&images->views[slot] != view)
util_copy_image_view(&images->views[slot], view);
si_set_shader_image_desc(ctx, view, skip_decompress, desc, NULL);
- if (res->b.b.target == PIPE_BUFFER) {
+ if (res->b.b.target == PIPE_BUFFER ||
+ view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) {
images->needs_color_decompress_mask &= ~(1 << slot);
res->bind_history |= PIPE_BIND_SHADER_IMAGE;
} else {
struct si_texture *tex = (struct si_texture *)res;
unsigned level = view->u.tex.level;
if (color_needs_decompression(tex)) {
images->needs_color_decompress_mask |= 1 << slot;
} else {
images->needs_color_decompress_mask &= ~(1 << slot);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 39152587a99..6765dcb3275 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -116,20 +116,22 @@
enum si_clear_code
{
DCC_CLEAR_COLOR_0000 = 0x00000000,
DCC_CLEAR_COLOR_0001 = 0x40404040,
DCC_CLEAR_COLOR_1110 = 0x80808080,
DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
DCC_CLEAR_COLOR_REG = 0x20202020,
DCC_UNCOMPRESSED = 0xFFFFFFFF,
};
+#define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
+
/* Debug flags. */
enum {
/* Shader logging options: */
DBG_VS = PIPE_SHADER_VERTEX,
DBG_PS = PIPE_SHADER_FRAGMENT,
DBG_GS = PIPE_SHADER_GEOMETRY,
DBG_TCS = PIPE_SHADER_TESS_CTRL,
DBG_TES = PIPE_SHADER_TESS_EVAL,
DBG_CS = PIPE_SHADER_COMPUTE,
DBG_NO_IR,
--
2.17.1
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