[Mesa-dev] Assorted bug fixes and improvements back-ported from an internal branch.

[Iago Toral]

With the few changes we agreed during the review this series is:

Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>

Jason, just in case you didn't follow: this series adds a regioning
lowering pass that will do exactly one of the things you suggested when
we were discussing how to improve handling of hardware restrictions in
the backend: it implements a FS IR lowering pass that addresses them
late after translation and optimization, which should also ensure that
other parts of the backend don't break things after translation, so I
think it is a good solution for at least some of the problems we
discussed.
 
Iago

On Sat, 2018-12-29 at 12:38 -0800, Francisco Jerez wrote:
> These are a number of fixes and clean-ups we've been carrying around
> for a while in an internal branch.  Most of the fixes are required
> for
> conformance of a future platform, but due to their nature some of
> them
> are likely to affect shipping platforms as well -- Especially the
> issues addressed by patches 1 and 5, and certainly the issue
> addressed
> by PATCH 2 which was causing Vulkan CTS failures on ICL.
> 
> PATCH 7 introduces a more automated approach to enforce any regioning
> restrictions of the hardware, which should be more reliable than the
> current approach of enforcing them manually at NIR translation time
> hoping that the optimizer will leave the workarounds untouched.  It
> has some potential to fix bugs in certain scenarios, but it's
> intrusive enough that it's not marked for inclusion in mesa-stable
> yet.
> 
> Patches 8-9 take advantage of the lowering pass in order to get rid
> of
> a bunch of code that is now redundant.  The code removed by PATCH 10
> has been redundant ever since the FS IR gained the ability to
> represent strided sources.
> 
> [PATCH 01/10] intel/fs: Handle source modifiers in
> lower_integer_multiplication().
> [PATCH 02/10] intel/fs: Implement quad swizzles on ICL+.
> [PATCH 03/10] intel/fs: Fix bug in lower_simd_width while splitting
> an instruction which was already split.
> [PATCH 04/10] intel/eu/gen7: Fix brw_MOV() with DF destination and
> strided source.
> [PATCH 05/10] intel/fs: Respect CHV/BXT regioning restrictions in
> copy propagation pass.
> [PATCH 06/10] intel/fs: Constify fs_inst::can_do_source_mods().
> [PATCH 07/10] intel/fs: Introduce regioning lowering pass.
> [PATCH 08/10] intel/fs: Remove existing lower_conversions pass.
> [PATCH 09/10] intel/fs: Remove nasty open-coded CHV/BXT 64-bit
> workarounds.
> [PATCH 10/10] intel/fs: Remove FS_OPCODE_UNPACK_HALF_2x16_SPLIT
> opcodes.
> 
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