[Mesa-dev] [PATCH v3 42/42] intel/compiler: allow propagating HF immediates to MAD/LRP

[Iago Toral Quiroga]

Even if we don't do 3-src algebraic optimizations for MAD and LRP in
the backend any more, the combine constants pass can still do a fine
job putting grouping these constants into single registers for better
register pressure.

v2:
 - updated comment to reference register pressure benefits rather than
   algebraic optimizations.
---
 src/intel/compiler/brw_fs_copy_propagation.cpp | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp
index 4e20ddb683a..5695678b766 100644
--- a/src/intel/compiler/brw_fs_copy_propagation.cpp
+++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
@@ -772,16 +772,14 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
 
       case BRW_OPCODE_MAD:
       case BRW_OPCODE_LRP:
-         /* 3-src instructions can't take IMM registers, however, for 32-bit
-          * floating instructions we rely on the combine constants pass to fix
-          * it up. For anything else, we shouldn't be promoting immediates
-          * until we can make the pass capable of combining constants of
-          * different sizes.
+         /* 3-src instructions can't take IMM registers, but we allow this
+          * here anyway and rely on the combine constants pass to fix it up
+          * later, hopefully leading to better register pressure.
           */
-         if (val.type == BRW_REGISTER_TYPE_F) {
-            inst->src[i] = val;
-            progress = true;
-         }
+         assert(val.type == BRW_REGISTER_TYPE_F ||
+                val.type == BRW_REGISTER_TYPE_HF);
+         inst->src[i] = val;
+         progress = true;
          break;
 
       default:
-- 
2.17.1