[Mesa-dev] [PATCH 2/2] radeonsi: unify error paths in si_texture_create_object

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_texture.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index a56674b6000..585f58c1e38 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1104,21 +1104,21 @@ si_texture_create_object(struct pipe_screen *screen,
 			 const struct pipe_resource *base,
 			 struct pb_buffer *buf,
 			 struct radeon_surf *surface)
 {
 	struct si_texture *tex;
 	struct r600_resource *resource;
 	struct si_screen *sscreen = (struct si_screen*)screen;
 
 	tex = CALLOC_STRUCT(si_texture);
 	if (!tex)
-		return NULL;
+		goto error;
 
 	resource = &tex->buffer;
 	resource->b.b = *base;
 	resource->b.b.next = NULL;
 	resource->b.vtbl = &si_texture_vtbl;
 	pipe_reference_init(&resource->b.b.reference, 1);
 	resource->b.b.screen = screen;
 
 	/* don't include stencil-only formats which we don't support for rendering */
 	tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format));
@@ -1179,48 +1179,44 @@ si_texture_create_object(struct pipe_screen *screen,
 			tex->fmask_offset = align64(tex->size,
 						     tex->surface.fmask_alignment);
 			tex->size = tex->fmask_offset + tex->surface.fmask_size;
 
 			/* Allocate CMASK. */
 			tex->cmask_offset = align64(tex->size, tex->surface.cmask_alignment);
 			tex->size = tex->cmask_offset + tex->surface.cmask_size;
 			tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
 			tex->cmask_buffer = &tex->buffer;
 
-			if (!tex->surface.fmask_size || !tex->surface.cmask_size) {
-				FREE(tex);
-				return NULL;
-			}
+			if (!tex->surface.fmask_size || !tex->surface.cmask_size)
+				goto error;
 		}
 
 		/* Shared textures must always set up DCC here.
 		 * If it's not present, it will be disabled by
 		 * apply_opaque_metadata later.
 		 */
 		if (tex->surface.dcc_size &&
 		    (buf || !(sscreen->debug_flags & DBG(NO_DCC))) &&
 		    !(tex->surface.flags & RADEON_SURF_SCANOUT)) {
 			/* Reserve space for the DCC buffer. */
 			tex->dcc_offset = align64(tex->size, tex->surface.dcc_alignment);
 			tex->size = tex->dcc_offset + tex->surface.dcc_size;
 		}
 	}
 
 	/* Now create the backing buffer. */
 	if (!buf) {
 		si_init_resource_fields(sscreen, resource, tex->size,
 					  tex->surface.surf_alignment);
 
-		if (!si_alloc_resource(sscreen, resource)) {
-			FREE(tex);
-			return NULL;
-		}
+		if (!si_alloc_resource(sscreen, resource))
+			goto error;
 	} else {
 		resource->buf = buf;
 		resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf);
 		resource->bo_size = buf->size;
 		resource->bo_alignment = buf->alignment;
 		resource->domains = sscreen->ws->buffer_get_initial_domain(resource->buf);
 		if (resource->domains & RADEON_DOMAIN_VRAM)
 			resource->vram_usage = buf->size;
 		else if (resource->domains & RADEON_DOMAIN_GTT)
 			resource->gart_usage = buf->size;
@@ -1268,20 +1264,24 @@ si_texture_create_object(struct pipe_screen *screen,
 		puts("Texture:");
 		struct u_log_context log;
 		u_log_context_init(&log);
 		si_print_texture_info(sscreen, tex, &log);
 		u_log_new_page_print(&log, stdout);
 		fflush(stdout);
 		u_log_context_destroy(&log);
 	}
 
 	return tex;
+
+error:
+	FREE(tex);
+	return NULL;
 }
 
 static enum radeon_surf_mode
 si_choose_tiling(struct si_screen *sscreen,
 		 const struct pipe_resource *templ, bool tc_compatible_htile)
 {
 	const struct util_format_description *desc = util_format_description(templ->format);
 	bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING;
 	bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
 				!(templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH);
-- 
2.17.1