[Mesa-dev] [PATCH] intel/fs: Don't apply the des stride alignment rule to accumulators
Jason Ekstrand
jason at jlekstrand.net
Thu Jan 17 15:19:36 UTC 2019
Bah... previous e-mail unfinished. Please ignore.
On Thu, Jan 17, 2019 at 4:15 AM Francisco Jerez <currojerez at riseup.net>
wrote:
> Jason Ekstrand <jason at jlekstrand.net> writes:
>
> > The pass was discovered to cause problems with the MUL+MACH combination
> > we emit for nir_[iu]mul_high. In an experimental branch of mine, I ran
> > into issues where the MUL+MACH ended up using a strided source due to
> > working on half of a uint64_t and the new lowering pass helpfully tried
> > to fix the multiply which wrote to an unstriated accumulator.
>
> > Not only did the multiply not need to be fixed
>
> That's far from clear, and inconsistent with what this patch is doing,
> since the fix is still being applied (Wouldn't it make sense to clarify
> that in the commit message since it's slightly misleading about it?).
>
> The original instruction was technically violating the first CHV/BXT
> double-precision regioning restriction before the pass was introduced,
> that's why it made any changes in the first place. The integer
> multiplication lowering code was just lucky enough that violating the
> restriction didn't matter in this case, but I doubt that the reason for
> that had anything to do with the accumulator being the explicit
> destination...
>
Explicit, no, but I do suspect that does have to do with it being the
accumulator. This restriction isn't theoretical; if you violate it with a
GRF, you will get data corruption; I've seen it myself. I could see two
possible explanations:
1. Under the hood the accumulator is written with a Q type and an internal
stride of 8 bytes, hence the restriction does apply but is implicitly
satisfied for D type source strides of 1 and 2.
2. The data path to the accumulator is a special case in the hardware and
doesn't use the normal general-purpose regioning logic and so doesn't
require the restriction.
I don't find the first one very convincing at all. Among other things, if
it were the true reason, it would imply that we would need to use a stride
of exactly 2 on D type sources which but empirical evidence suggests that
"mul(8) acc0<1> g5<8,8,1>UD g9<16,8,2>UW" works just fine.
> > but the "fix" ended up breaking it because a MOV to the accumulator is
> > not the same as using it as a multiply destination due to the magic
> > way the 33/64 bits of the
>
> Technically it has 66 bits (it wasn't a typo when I said that to you
> earlier on IRC). That's how it can t hold the result of a SIMD16
> 16x16-bit integer multiplication with 33-bit signed precision per scalar
> component.
>
Yes, there are 33 bits available for WxW multiplies but this is dealing
with a DxD multiply which only has 64 bits according to this bit of bspec
text:
As there are only 64 bits per channel in DWord mode (D and UD), it is
sufficient to store the multiplication result of two DWord operands as long
as the post source modified sources are still within 32 bits. If any one
source is type UD and is negated, the negated result becomes 33 bits. The
DWord multiplication result is then 65 bits, bigger than the storage
capacity of accumulators. Consequently, the results are unpredictable.
> > accumulator are handled for different instruction types.
> >
> > Fixes: efa4e4bc5fc "intel/fs: Introduce regioning lowering pass"
> > Cc: Francisco Jerez <currojerez at riseup.net>
> > ---
> > src/intel/compiler/brw_fs_lower_regioning.cpp | 16 +++++++++++++++-
> > 1 file changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/intel/compiler/brw_fs_lower_regioning.cpp
> b/src/intel/compiler/brw_fs_lower_regioning.cpp
> > index cc4163b4c2c..b8a89e82272 100644
> > --- a/src/intel/compiler/brw_fs_lower_regioning.cpp
> > +++ b/src/intel/compiler/brw_fs_lower_regioning.cpp
> > @@ -53,7 +53,13 @@ namespace {
> > unsigned
> > required_dst_byte_stride(const fs_inst *inst)
> > {
> > - if (type_sz(inst->dst.type) < get_exec_type_size(inst) &&
> > + if (inst->dst.is_accumulator()) {
> > + /* Even though it's not explicitly documented in the PRMs or
> the
> > + * BSpec, writes to the accumulator appear to not need any
> special
> > + * treatment with respect too their destination stride
> alignment.
> > + */
>
> The code is not really doing what the comment says. The
> destination/source stride alignment restriction will still be honored
> for this instruction. It's just that the destination *has* to be left
> untouched while doing that in the case of an integer MUL/MACH
> instruction (that's the only reason I asked you to return the original
> byte stride of the destination), because splitting off the region into a
> MOV would lead to data loss due to the inconsistent semantics of the
> accumulator destination for integer MUL/MACH (which update the whole 66
> bits) and every other integer arithmetic instruction (which update the
> bottom 33 bits and *apparently* leave the top 33 bits uninitialized) --
> IOW this is only here so that the assert below doesn't fire.
>
Ok, now I'm very confused. It sounds to me like you still think it's
broken but it's less broken than a MOV to acc0 so we should just go with
it? That's very disconcerting.... If there's more investigation you'd
like to see done, I'm willing to poke at it a bit more and see if we can
get a better understanding.
> > + return inst->dst.stride * type_sz(inst->dst.type);
> > + } else if (type_sz(inst->dst.type) < get_exec_type_size(inst) &&
>
> The code changes themselves are just as I wished, so this gets my:
>
> Reviewed-by: Francisco Jerez <currojerez at riseup.net>
>
> assuming that you clarify the commit message and comment above.
>
I agree that the commit message above was a bit terse but it's entirely
unclear what it *should* say. How about something like this:
BEGIN COMMITMSG
In some shaders, you can end up with a stride in the source of a
SHADER_OPCODE_MULH. One way this can happen is if the MULH is acting on
the top bits of a 64-bit value due to 64-bit integer lowering. In this
case, the compiler will produce something like this:
mul(8) acc0<1>UD g5<8,4,2>UD 0x0004UW { align1 1Q
};
mach(8) g6<1>UD g5<8,4,2>UD 0x00000004UD { align1 1Q
AccWrEnable };
The new region fixup pass looks at the MUL and sees a strided source and
unstrided destination and determines that the sequence is illegal. It then
attempts to fix the illegal stride by replacing the destination of the MUL
with a temporary and emitting a MOV into the accumulator:
mul(8) g9<2>UD g5<8,4,2>UD 0x0004UW { align1 1Q
};
mov(8) acc0<1>UD g9<8,4,2>UD { align1 1Q
};
mach(8) g6<1>UD g5<8,4,2>UD 0x00000004UD { align1 1Q
AccWrEnable };
Unfortunately, this new sequence isn't correct because MOV accesses the
accumulator with a different precision to MUL and, instead of filling the
bottom 32 bits with the source and zeroing the top 32 bits, it leaves the
top 32 (or maybe 31) bits alone and full of garbage. When the MACH comes
along and tries to complete the multiplication, the result is correct in
the bottom 32 bits (which we throw away) and garbage in the top 32 bits
which are actually returned by MACH.
This commit does two things: First, it adds an assert to ensure that we
don't try to rewrite accumulator destinations of MUL instructions so we can
avoid this precision issue. Second, it modifies required_dst_byte_stride
to require a tightly packed stride so that we fix up the sources instead
and the actual code which gets emitted is this:
mov(8) g9<1>UD g5<8,4,2>UD { align1 1Q
};
mul(8) acc0<1>UD g9<8,8,1>UD 0x0004UW { align1 1Q
};
mach(8) g6<1>UD g5<8,4,2>UD 0x00000004UD { align1 1Q
AccWrEnable };
END COMMITMSG
Is that a better commit message?
You may be saying to yourself, "See, the working code has an unstrided
source because we fix the source; the restriction still applies" Well... I
tried that too... I modified the fixup pass to just completely ignore the
restriction if it has an accumulator destination and it emits the following:
mul(8) acc0<1>UD g5<8,4,2>UD 0x0004UW { align1 1Q
};
mach(8) g6<1>UD g5<8,4,2>UD 0x00000004UD { align1 1Q
AccWrEnable };
which works perfectly well. I suspect that the source strides still have
to match but I really don't think the hardware cares about the destination
stride when it's an accumulator.
--Jason
> > !is_byte_raw_mov(inst)) {
> > return get_exec_type_size(inst);
> > } else {
> > @@ -316,6 +322,14 @@ namespace {
> > bool
> > lower_dst_region(fs_visitor *v, bblock_t *block, fs_inst *inst)
> > {
> > + /* We cannot replace the result of an integer multiply which
> writes the
> > + * accumulator because MUL+MACH pairs act on the accumulator as a
> 64-bit
> > + * value whereas the MOV will act on only 32 or 33 bits of the
> > + * accumulator.
> > + */
> > + assert(inst->opcode != BRW_OPCODE_MUL ||
> !inst->dst.is_accumulator() ||
> > + brw_reg_type_is_floating_point(inst->dst.type));
> > +
> > const fs_builder ibld(v, block, inst);
> > const unsigned stride = required_dst_byte_stride(inst) /
> > type_sz(inst->dst.type);
> > --
> > 2.20.1
>
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