[Mesa-dev] [PATCH v3 03/42] intel/compiler: split float to 64-bit opcodes from int to 64-bit

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

On Tue, Jan 15, 2019 at 7:55 AM Iago Toral Quiroga <itoral at igalia.com>
wrote:

> Going forward having these split is a bit more convenient since these two
> groups have different restrictions.
>
> v2:
>  - Rebased on top of new regioning lowering pass.
>
> Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com> (v1)
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index bdc883e5364..a59debf2b78 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -801,10 +801,17 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
>     case nir_op_f2f64:
>     case nir_op_f2i64:
>     case nir_op_f2u64:
> +      assert(type_sz(op[0].type) > 2); /* brw_nir_lower_conversions */
> +      inst = bld.MOV(result, op[0]);
> +      inst->saturate = instr->dest.saturate;
> +      break;
> +
>     case nir_op_i2f64:
>     case nir_op_i2i64:
>     case nir_op_u2f64:
>     case nir_op_u2u64:
> +      assert(type_sz(op[0].type) > 1); /* brw_nir_lower_conversions */
> +      /* fallthrough */
>     case nir_op_f2f32:
>     case nir_op_f2i32:
>     case nir_op_f2u32:
> --
> 2.17.1
>
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