[Mesa-dev] [PATCH v3 00/42] intel: VK_KHR_shader_float16_int8 implementation
Iago Toral
itoral at igalia.com
Fri Jan 18 11:37:38 UTC 2019
Thanks a lot of for all the review work! When you're done reviewing all
the patches I'll prepare a v4 with all the changes.
On Thu, 2019-01-17 at 18:24 -0600, Jason Ekstrand wrote:
> I'm done for the day but I've read through most of the patches. I
> think I've got 4 or 5 tricky ones left. By and large, I think things
> are looking really good. I don't know that we'll make 19.0 but
> there's a possibility. If not, it'll likely land shortly after.
>
> On Tue, Jan 15, 2019 at 7:54 AM Iago Toral Quiroga <itoral at igalia.com
> > wrote:
> > The changes in this version address review feedback to v2 and, most
> > importantly,
> >
> > rebase on top of relevant changes in master, specifically Curro's
> > regioning
> >
> > lowering pass. This new regioning pass simplifies some of the NIR
> > translation
> >
> > code (specifically the code for translating regioning restrictions
> > on
> >
> > conversions for atom platforms) making some of the previous work in
> > this series
> >
> > unnecessary. The regioning restrictions for conversions between
> > integer and
> >
> > half-float added with this series are are now implemented as part
> > of this
> >
> > framework instead of doing it at NIR translation time. This version
> > of the
> >
> > series also dropped the SPIR-V compiler patches that have already
> > been merged.
> >
> >
> >
> > As always, a branch for with these patches is available for testing
> > in the
> >
> > itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa
> > repository at
> >
> > https://github.com/Igalia/mesa.
> >
> >
> >
> > Iago Toral Quiroga (42):
> >
> > intel/compiler: handle conversions between int and half-float on
> > atom
> >
> > intel/compiler: add a NIR pass to lower conversions
> >
> > intel/compiler: split float to 64-bit opcodes from int to 64-bit
> >
> > intel/compiler: handle b2i/b2f with other integer conversion
> > opcodes
> >
> > intel/compiler: assert restrictions on conversions to half-float
> >
> > intel/compiler: lower some 16-bit float operations to 32-bit
> >
> > intel/compiler: lower 16-bit extended math to 32-bit prior to
> > gen9
> >
> > intel/compiler: implement 16-bit fsign
> >
> > intel/compiler: allow extended math functions with HF operands
> >
> > compiler/nir: add lowering option for 16-bit fmod
> >
> > intel/compiler: lower 16-bit fmod
> >
> > compiler/nir: add lowering for 16-bit flrp
> >
> > intel/compiler: lower 16-bit flrp
> >
> > compiler/nir: add lowering for 16-bit ldexp
> >
> > intel/compiler: Extended Math is limited to SIMD8 on half-float
> >
> > intel/compiler: add instruction setters for Src1Type and
> > Src2Type.
> >
> > intel/compiler: add new half-float register type for 3-src
> >
> > instructions
> >
> > intel/compiler: add a helper function to query hardware type
> > table
> >
> > intel/compiler: don't compact 3-src instructions with Src1Type or
> >
> > Src2Type bits
> >
> > intel/compiler: allow half-float on 3-source instructions since
> > gen8
> >
> > intel/compiler: set correct precision fields for 3-source float
> >
> > instructions
> >
> > intel/compiler: don't propagate HF immediates to 3-src
> > instructions
> >
> > intel/compiler: fix ddx and ddy for 16-bit float
> >
> > intel/compiler: fix ddy for half-float in gen8
> >
> > intel/compiler: workaround for SIMD8 half-float MAD in gen8
> >
> > intel/compiler: split is_partial_write() into two variants
> >
> > intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
> >
> > intel/compiler: handle 64-bit float to 8-bit integer conversions
> >
> > intel/compiler: handle conversions between int and half-float on
> > atom
> >
> > intel/compiler: implement isign for int8
> >
> > intel/compiler: ask for an integer type if requesting an 8-bit
> > type
> >
> > intel/eu: force stride of 2 on NULL register for Byte
> > instructions
> >
> > compiler/spirv: add support for Float16 and Int8 capabilities
> >
> > anv/pipeline: support Float16 and Int8 capabilities in gen8+
> >
> > anv/device: expose shaderFloat16 and shaderInt8 in gen8+
> >
> > intel/compiler: implement is_zero, is_one, is_negative_one for
> >
> > 8-bit/16-bit
> >
> > intel/compiler: add a brw_reg_type_is_integer helper
> >
> > intel/compiler: fix cmod propagation for non 32-bit types
> >
> > intel/compiler: remove MAD/LRP algebraic optimizations from the
> >
> > backend
> >
> > intel/compiler: support half-float in the combine constants pass
> >
> > intel/compiler: fix combine constants for Align16 with half-float
> >
> > prior to gen9
> >
> > intel/compiler: allow propagating HF immediates to MAD/LRP
> >
> >
> >
> > src/compiler/nir/nir.h | 2 +
> >
> > src/compiler/nir/nir_opt_algebraic.py | 11 +-
> >
> > src/compiler/shader_info.h | 2 +
> >
> > src/compiler/spirv/spirv_to_nir.c | 8 +-
> >
> > src/intel/Makefile.sources | 1 +
> >
> > src/intel/compiler/brw_compiler.c | 2 +
> >
> > src/intel/compiler/brw_eu_compact.c | 5 +-
> >
> > src/intel/compiler/brw_eu_emit.c | 36 +++-
> >
> > src/intel/compiler/brw_fs.cpp | 143 ++++++++++--
> > ----
> >
> > src/intel/compiler/brw_fs.h | 1 +
> >
> > .../compiler/brw_fs_cmod_propagation.cpp | 34 ++--
> >
> > .../compiler/brw_fs_combine_constants.cpp | 82 +++++++--
> >
> > .../compiler/brw_fs_copy_propagation.cpp | 14 +-
> >
> > src/intel/compiler/brw_fs_cse.cpp | 3 +-
> >
> > .../compiler/brw_fs_dead_code_eliminate.cpp | 2 +-
> >
> > src/intel/compiler/brw_fs_generator.cpp | 47 +++---
> >
> > src/intel/compiler/brw_fs_live_variables.cpp | 2 +-
> >
> > src/intel/compiler/brw_fs_nir.cpp | 85 ++++++++--
> >
> > src/intel/compiler/brw_fs_reg_allocate.cpp | 2 +-
> >
> > .../compiler/brw_fs_register_coalesce.cpp | 2 +-
> >
> > .../compiler/brw_fs_saturate_propagation.cpp | 7 +-
> >
> > src/intel/compiler/brw_fs_sel_peephole.cpp | 4 +-
> >
> > src/intel/compiler/brw_inst.h | 2 +
> >
> > src/intel/compiler/brw_ir_fs.h | 36 +++-
> >
> > src/intel/compiler/brw_nir.c | 21 ++-
> >
> > src/intel/compiler/brw_nir.h | 2 +
> >
> > .../compiler/brw_nir_lower_conversions.c | 158
> > ++++++++++++++++++
> >
> > src/intel/compiler/brw_reg_type.c | 70 +++++---
> >
> > src/intel/compiler/brw_reg_type.h | 18 ++
> >
> > src/intel/compiler/brw_shader.cpp | 26 +++
> >
> > src/intel/compiler/meson.build | 1 +
> >
> > src/intel/vulkan/anv_device.c | 9 +
> >
> > src/intel/vulkan/anv_extensions.py | 1 +
> >
> > src/intel/vulkan/anv_pipeline.c | 2 +
> >
> > 34 files changed, 674 insertions(+), 167 deletions(-)
> >
> > create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
> >
> >
> >
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