[Mesa-dev] [PATCH] intel/genxml: add missing MI_PREDICATE compare operations

[Rafael Antognolli]

Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>

On Fri, Jan 18, 2019 at 05:01:58PM +0000, Lionel Landwerlin wrote:
> Doesn't save us a great deal of lines but at least they get decoded in
> aubinators.
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> ---
>  src/intel/genxml/gen10.xml         | 2 ++
>  src/intel/genxml/gen11.xml         | 2 ++
>  src/intel/genxml/gen7.xml          | 2 ++
>  src/intel/genxml/gen75.xml         | 2 ++
>  src/intel/genxml/gen8.xml          | 2 ++
>  src/intel/genxml/gen9.xml          | 2 ++
>  src/intel/vulkan/genX_cmd_buffer.c | 1 -
>  7 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
> index 9ec311d6cc5..7043ab8995d 100644
> --- a/src/intel/genxml/gen10.xml
> +++ b/src/intel/genxml/gen10.xml
> @@ -3047,6 +3047,8 @@
>        <value name="XOR" value="3"/>
>      </field>
>      <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
> +      <value name="TRUE" value="0"/>
> +      <value name="FALSE" value="1"/>
>        <value name="SRCS_EQUAL" value="2"/>
>        <value name="DELTAS_EQUAL" value="3"/>
>      </field>
> diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
> index 6ab1f965650..3af80a6ed3d 100644
> --- a/src/intel/genxml/gen11.xml
> +++ b/src/intel/genxml/gen11.xml
> @@ -3042,6 +3042,8 @@
>        <value name="XOR" value="3"/>
>      </field>
>      <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
> +      <value name="TRUE" value="0"/>
> +      <value name="FALSE" value="1"/>
>        <value name="SRCS_EQUAL" value="2"/>
>        <value name="DELTAS_EQUAL" value="3"/>
>      </field>
> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
> index 893c12b8af9..3c445757300 100644
> --- a/src/intel/genxml/gen7.xml
> +++ b/src/intel/genxml/gen7.xml
> @@ -2051,6 +2051,8 @@
>        <value name="XOR" value="3"/>
>      </field>
>      <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
> +      <value name="TRUE" value="0"/>
> +      <value name="FALSE" value="1"/>
>        <value name="SRCS_EQUAL" value="2"/>
>        <value name="DELTAS_EQUAL" value="3"/>
>      </field>
> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
> index 009a123ad69..3df7dc29939 100644
> --- a/src/intel/genxml/gen75.xml
> +++ b/src/intel/genxml/gen75.xml
> @@ -2462,6 +2462,8 @@
>        <value name="XOR" value="3"/>
>      </field>
>      <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
> +      <value name="TRUE" value="0"/>
> +      <value name="FALSE" value="1"/>
>        <value name="SRCS_EQUAL" value="2"/>
>        <value name="DELTAS_EQUAL" value="3"/>
>      </field>
> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> index fd19b0c8b33..4d1488dae62 100644
> --- a/src/intel/genxml/gen8.xml
> +++ b/src/intel/genxml/gen8.xml
> @@ -2690,6 +2690,8 @@
>        <value name="XOR" value="3"/>
>      </field>
>      <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
> +      <value name="TRUE" value="0"/>
> +      <value name="FALSE" value="1"/>
>        <value name="SRCS_EQUAL" value="2"/>
>        <value name="DELTAS_EQUAL" value="3"/>
>      </field>
> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
> index 706d398babb..3f02e866d0c 100644
> --- a/src/intel/genxml/gen9.xml
> +++ b/src/intel/genxml/gen9.xml
> @@ -2973,6 +2973,8 @@
>        <value name="XOR" value="3"/>
>      </field>
>      <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
> +      <value name="TRUE" value="0"/>
> +      <value name="FALSE" value="1"/>
>        <value name="SRCS_EQUAL" value="2"/>
>        <value name="DELTAS_EQUAL" value="3"/>
>      </field>
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
> index 6fb19661ebb..544e2929990 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -3310,7 +3310,6 @@ void genX(CmdDispatchIndirect)(
>     }
>  
>     /* predicate = !predicate; */
> -#define COMPARE_FALSE                           1
>     anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
>        mip.LoadOperation    = LOAD_LOADINV;
>        mip.CombineOperation = COMBINE_OR;
> -- 
> 2.20.1
> 
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