[Mesa-dev] [PATCH] intel/compiler: Reset default flag register in brw_find_live_channel()

[Francisco Jerez]

Matt Turner <mattst88 at gmail.com> writes:

> emit_uniformize() emits SHADER_OPCODE_FIND_LIVE_CHANNEL with its
> flag_subreg set, so that the IR knows which flag is accessed. However
> the flag is only used on Gen7 in Align1 mode.
>
> To avoid setting unnecessary bits in the instruction words, get the
> information we need and reset the default flag register. This allows
> round-tripping through the assembler/disassembler.
> ---
>  src/intel/compiler/brw_eu_emit.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
> index 45e2552783b..d05ea506353 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -3312,6 +3312,14 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst,
>  
>     brw_push_insn_state(p);
>  
> +   /* The flag register is only used on Gen7 in align1 mode, so avoid setting
> +    * unnecessary bits in the instruction words, get the information we need
> +    * and reset the default flag register.
> +    */
> +   int flag_reg = p->current->flag_subreg / 2;
> +   int flag_subreg = p->current->flag_subreg % 2;

You can replace the two lines above with:

+ const unsigned flag_subreg = p->current->flag_subreg;

> +   brw_set_default_flag_reg(p, 0, 0);
> +
>     if (brw_get_default_access_mode(p) == BRW_ALIGN_1) {
>        brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>  
> @@ -3345,12 +3353,14 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst,
>            */
>           inst = brw_FBL(p, vec1(dst), exec_mask);
>        } else {
> -         const struct brw_reg flag = brw_flag_reg(p->current->flag_subreg / 2,
> -                                                  p->current->flag_subreg % 2);
> +         const struct brw_reg flag = brw_flag_reg(flag_reg, flag_subreg);

so this will just be "brw_flag_subreg(flag_subreg)".

>  
>           brw_set_default_exec_size(p, BRW_EXECUTE_1);
>           brw_MOV(p, retype(flag, BRW_REGISTER_TYPE_UD), brw_imm_ud(0));
>  
> +         brw_push_insn_state(p);
> +         brw_set_default_flag_reg(p, flag_reg, flag_subreg);
> +

No need to push and pop another entry into the default instruction state
stack, you can just "brw_inst_set_flag_*reg_nr()" on the MOV instruction.

>           /* Run enough instructions returning zero with execution masking and
>            * a conditional modifier enabled in order to get the full execution
>            * mask in f1.0.  We could use a single 32-wide move here if it
> @@ -3368,6 +3378,8 @@ brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst,
>              brw_inst_set_exec_size(devinfo, inst, cvt(lower_size) - 1);
>           }
>  
> +         brw_pop_insn_state(p);
> +
>           /* Find the first bit set in the exec_size-wide portion of the flag
>            * register that was updated by the last sequence of MOV
>            * instructions.
> -- 
> 2.19.2
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