[Mesa-dev] [PATCH] nvc0: don't put text segment into bufctx
Ilia Mirkin
imirkin at alum.mit.edu
Wed Jan 23 04:20:42 UTC 2019
The text segment is shared among multiple contexts, while each one has
its own bufctx. So when reallocating the text segment, some contexts may
end up with stale values in their bufctx's. Instead limit the exposure
to the bufctx to within a single draw.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
nv50 doesn't resize its code segment. Karol -- this is slightly
different than the patch you tested earlier.
src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 5 ++++-
src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 2 --
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 10 ----------
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 3 +++
src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 5 +++++
src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 3 +++
6 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index 4963493877b..1bd1732c8d5 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -423,6 +423,7 @@ void
nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
{
struct nvc0_context *nvc0 = nvc0_context(pipe);
+ struct nvc0_screen *screen = nvc0->screen;
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_program *cp = nvc0->compprog;
int ret;
@@ -463,12 +464,14 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
PUSH_DATA (push, (info->block[1] << 16) | info->block[0]);
PUSH_DATA (push, info->block[2]);
+ nouveau_pushbuf_space(push, 16, 2, 1);
+ PUSH_REFN(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
+
if (unlikely(info->indirect)) {
struct nv04_resource *res = nv04_resource(info->indirect);
uint32_t offset = res->offset + info->indirect_offset;
unsigned macro = NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT;
- nouveau_pushbuf_space(push, 16, 0, 1);
PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
PUSH_DATA(push, NVC0_FIFO_PKHDR_1I(1, macro, 3));
nouveau_pushbuf_data(push, res->bo, offset,
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
index 08ca0a204d3..356016c7225 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c
@@ -449,11 +449,9 @@ nvc0_create(struct pipe_screen *pscreen, void *priv, unsigned ctxflags)
flags = NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD;
- BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT, flags, screen->text);
BCTX_REFN_bo(nvc0->bufctx_3d, 3D_SCREEN, flags, screen->uniform_bo);
BCTX_REFN_bo(nvc0->bufctx_3d, 3D_SCREEN, flags, screen->txc);
if (screen->compute) {
- BCTX_REFN_bo(nvc0->bufctx_cp, CP_TEXT, flags, screen->text);
BCTX_REFN_bo(nvc0->bufctx_cp, CP_SCREEN, flags, screen->uniform_bo);
BCTX_REFN_bo(nvc0->bufctx_cp, CP_SCREEN, flags, screen->txc);
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 57d98753f45..1bbfa4a9428 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -831,16 +831,6 @@ nvc0_program_upload(struct nvc0_context *nvc0, struct nvc0_program *prog)
NOUVEAU_ERR("Error allocating TEXT area: %d\n", ret);
return false;
}
- nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
- BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT,
- NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
- screen->text);
- if (screen->compute) {
- nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEXT);
- BCTX_REFN_bo(nvc0->bufctx_cp, CP_TEXT,
- NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
- screen->text);
- }
/* Re-upload the builtin function into the new code segment. */
nvc0_program_library_upload(nvc0);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index ccfe7ffb18b..c4d64c134c1 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -1178,6 +1178,7 @@ nvc0_blitctx_post_blit(struct nvc0_blitctx *blit)
nvc0->cond_cond, nvc0->cond_mode);
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX_TMP);
+ nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 0));
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(4, 1));
@@ -1301,6 +1302,8 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP,
NOUVEAU_BO_GART | NOUVEAU_BO_RD, vtxbuf_bo);
+ BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT, vram_domain | NOUVEAU_BO_RD,
+ screen->text);
nouveau_pushbuf_validate(push);
BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 4);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
index 66de6d9e2fa..3fbe7614e52 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
@@ -919,6 +919,7 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
struct nvc0_context *nvc0 = nvc0_context(pipe);
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_screen *screen = nvc0->screen;
+ unsigned vram_domain = NV_VRAM_DOMAIN(&screen->base);
int s;
/* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
@@ -982,6 +983,9 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
resident->flags);
}
+ BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT, vram_domain | NOUVEAU_BO_RD,
+ screen->text);
+
nvc0_state_validate_3d(nvc0, ~0);
if (nvc0->vertprog->vp.need_draw_parameters && !info->indirect) {
@@ -1092,6 +1096,7 @@ cleanup:
nouveau_pushbuf_bufctx(push, NULL);
+ nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_IDX);
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS);
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
index 8aa8d4936f3..2a84215048b 100644
--- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
@@ -696,6 +696,7 @@ void
nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
{
struct nvc0_context *nvc0 = nvc0_context(pipe);
+ struct nvc0_screen *screen = nvc0->screen;
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
void *desc;
uint64_t desc_gpuaddr;
@@ -769,6 +770,8 @@ nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
}
/* upload descriptor and flush */
+ nouveau_pushbuf_space(push, 6, 1, 0);
+ PUSH_REFN(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1);
PUSH_DATA (push, desc_gpuaddr >> 8);
BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1);
--
2.19.2
More information about the mesa-dev
mailing list