[Mesa-dev] [MR] intel: Skip bit6 swizzle test in Gen8+

[Caio Marcelo de Oliveira Filho]

https://gitlab.freedesktop.org/mesa/mesa/merge_requests/188

Per Broadwell PRM, we can skip the bit6 swizzle check and just assume false.

    "Tiled Channel Select Decision

    Before Gen8, there was a historical configuration control field to
    swizzle address bit[6] for in X/Y tiling modes. This was set in
    three different places: TILECTL[1:0], ARB_MODE[5:4], and
    DISP_ARB_CTL[14:13].

    For Gen8 and subsequent generations, the swizzle fields are all
    reserved, and the CPU's memory controller performs all address
    swizzling modifications."

MR originated from a conversation with Ken.

Caio Marcelo de Oliveira Filho (3):
      i965: skip bit6 swizzle detection in Gen8+
      anv: skip bit6 swizzle detection in Gen8+
      isl: assert that Gen8+ don't have bit6_swizzling

Series diff --stat

 src/intel/isl/isl.c                      |  3 +++
 src/intel/vulkan/anv_device.c            | 16 ++++++++++++++--
 src/mesa/drivers/dri/i965/intel_screen.c | 14 ++++++++++++++
 3 files changed, 31 insertions(+), 2 deletions(-)