[Mesa-dev] [PATCH 5/8] radv/gfx10: emit GE_PC_ALLOC

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/amd/vulkan/radv_pipeline.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 63583a9c6d9..fdb0ed29ea4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3265,6 +3265,18 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
 	radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
 }
 
+static void
+gfx10_set_ge_pc_alloc(struct radeon_cmdbuf *ctx_cs,
+		      struct radv_pipeline *pipeline,
+		      bool culling)
+{
+	struct radeon_info *info = &pipeline->device->physical_device->rad_info;
+
+	radeon_set_uconfig_reg(ctx_cs, R_030980_GE_PC_ALLOC,
+			       S_030980_OVERSUB_EN(1) |
+			       S_030980_NUM_PC_LINES((culling ? 256 : 128) * info->max_se - 1));
+}
+
 static void
 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
 			     struct radeon_cmdbuf *cs,
@@ -3331,6 +3343,9 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
 	if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
 		radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
 		                       outinfo->writes_viewport_index);
+
+	if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
+		gfx10_set_ge_pc_alloc(ctx_cs, pipeline, false);
 }
 
 static void
@@ -3477,6 +3492,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
 			       S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
 			       S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
 			       S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
+
+	gfx10_set_ge_pc_alloc(ctx_cs, pipeline, false);
 }
 
 static void
-- 
2.22.0