[Mesa-dev] [Bug 109919] radv is broken on SI

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=109919

            Bug ID: 109919
           Summary: radv is broken on SI
           Product: Mesa
           Version: git
          Hardware: Other
                OS: Linux (All)
            Status: NEW
          Severity: major
          Priority: medium
         Component: Drivers/Vulkan/radeon
          Assignee: mesa-dev at lists.freedesktop.org
          Reporter: turo.lamminen at alternativegames.net
        QA Contact: mesa-dev at lists.freedesktop.org

Created attachment 143552
  --> https://bugs.freedesktop.org/attachment.cgi?id=143552&action=edit
Vulkaninfo output

Any vulkan program that tries to draw something crashes on startup. Tested with
Sascha Willems triangle demo. vulkaninfo works.

GPU is Pitcairn.
LLVM is 1:9~svn354947-1~exp1+0~20190227014232.2351~1.gbpd90386
Kernel is 4.19.0-2-amd64 #1 SMP Debian 4.19.16-1 (2019-01-17)


Error message:

NIR validation failed in internal shader
1 errors:
shader: MESA_SHADER_COMPUTE
name: meta_clear_htile_mask
local-size: 64, 1, 1
shared-size: 0
inputs: 0
outputs: 0
uniforms: 0
shared: 0
decl_function main (0 params)

impl main {
        block block_0:
        /* preds: */
        vec3 32 ssa_0 = intrinsic load_local_invocation_id () ()
        vec3 32 ssa_1 = intrinsic load_work_group_id () ()
        vec4 32 ssa_2 = load_const (0x00000040 /* 0.000000 */, 0x00000001 /*
0.000000 */, 0x00000001 /* 0.000000 */, 0x00000000 /* 0.000000 */)
        vec4 32 ssa_3 = imul ssa_1.xyzz, ssa_2
        vec4 32 ssa_4 = iadd ssa_3, ssa_0.xyzz
        vec1 32 ssa_5 = load_const (0x00000010 /* 0.000000 */)
        vec4 32 ssa_6 = imul ssa_4, ssa_5.xxxx
        vec1 32 ssa_7 = imov ssa_6.x
        vec1 32 ssa_8 = load_const (0x00000000 /* 0.000000 */)
        vec1 32 ssa_9 = intrinsic vulkan_resource_index (ssa_8) (0, 0, 0) /*
desc-set=0 */ /* binding=0 */ /* desc_type=sampler */
error: components_written > 0 (../src/compiler/nir/nir_validate.c:569)

        vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */)
        /* constants */ vec2 32 ssa_11 = intrinsic load_push_constant (ssa_10)
(0, 8) /* base=0 */ /* range=8 */
        vec4 32 ssa_12 = intrinsic load_ssbo (ssa_9, ssa_7) (0, 0, 0) /*
access=0 */ /* align_mul=0 */ /* align_offset=0 */
        vec1 32 ssa_13 = imov /* constants */ ssa_11.y
        vec4 32 ssa_14 = iand ssa_12, ssa_13.xxxx
        vec1 32 ssa_15 = imov /* constants */ ssa_11.x
        vec4 32 ssa_16 = ior ssa_14, ssa_15.xxxx
        intrinsic store_ssbo (ssa_16, ssa_9, ssa_7) (15, 0, 0, 0) /*
wrmask=xyzw */ /* access=0 */ /* align_mul=0 */ /* align_offset=0 */
        /* succs: block_1 */
        block block_1:
}

Aborted


Bisected to:


61e009d2c4e4dfc071185f9e9c6366bc53168019 is the first bad commit
commit 61e009d2c4e4dfc071185f9e9c6366bc53168019
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Sat Jan 12 10:58:33 2019 -0600

    spirv: Use the same types for resource indices as pointers

    We need more space than just a 32-bit scalar and we have to burn all
    that space anyway so we may as well expose it to the driver.  This also
    fixes a subtle bug when UBOs and SSBOs have different pointer types.

    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

:040000 040000 b762d1ec1d9ce38e38c24d0e9ebe9154670060fd
c5367d0304364781650593f3a79721577eb08842 M      src

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