[Mesa-dev] [PATCH] intel/compiler: Print quad value in hex format

[Sagar Ghuge]

Please ignore this patch. Somehow my emails are getting delayed.

This is just a duplicate of the other patch which is on mailing list. 

On 3/24/19 10:19 AM, Sagar Ghuge wrote:
> From: Sagar Ghuge <sagar.ghuge at intel.com>
> 
> Print quad value same as unsigned quad so that we can distinguish in
> between quater control disassembled values for e.g 1/2/3[Q] and
> immediate quad value for e.g 1Q. This allows round-tripping through the
> assembler/disassembler.
> 
> Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
> ---
>  src/intel/compiler/brw_disasm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
> index efca3e2ce7d..04efa965cef 100644
> --- a/src/intel/compiler/brw_disasm.c
> +++ b/src/intel/compiler/brw_disasm.c
> @@ -1309,7 +1309,7 @@ imm(FILE *file, const struct gen_device_info *devinfo, enum brw_reg_type type,
>        format(file, "0x%016"PRIx64"UQ", brw_inst_imm_uq(devinfo, inst));
>        break;
>     case BRW_REGISTER_TYPE_Q:
> -      format(file, "%"PRId64"Q", brw_inst_imm_uq(devinfo, inst));
> +      format(file, "0x%016"PRIx64"Q", brw_inst_imm_uq(devinfo, inst));
>        break;
>     case BRW_REGISTER_TYPE_UD:
>        format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));
>