[Mesa-dev] [PATCH] radv: skip updating clear/color metadata for conditional rendering

[Samuel Pitoiset]

On 3/28/19 12:31 PM, Bas Nieuwenhuizen wrote:
> r-b, though technically you may want something older for the fixes tag.

Pushed with a "cc 19.0" tag instead.

>
> On Thu, Mar 28, 2019 at 12:20 PM Samuel Pitoiset
> <samuel.pitoiset at gmail.com> wrote:
>> I don't think we should update metadata when conditional rendering
>> is enabled. For some reasons, some CTS breaks only on SI.
>>
>> This fixes the following CTS on SI:
>> dEQP-VK.conditional_rendering.draw_clear.clear.depth.*
>>
>> Fixes: a777c3d7cb0 ("radv: Use correct image view comparison for fast clears.")
>> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
>> ---
>>   src/amd/vulkan/radv_cmd_buffer.c | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
>> index fdf3024147d..bed899d686e 100644
>> --- a/src/amd/vulkan/radv_cmd_buffer.c
>> +++ b/src/amd/vulkan/radv_cmd_buffer.c
>> @@ -1275,7 +1275,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
>>          if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
>>                  ++reg_count;
>>
>> -       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
>> +       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
>>          radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
>>                          S_370_WR_CONFIRM(1) |
>>                          S_370_ENGINE_SEL(V_370_PFP));
>> @@ -1299,7 +1299,7 @@ radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
>>          uint64_t va = radv_buffer_get_va(image->bo);
>>          va += image->offset + image->tc_compat_zrange_offset;
>>
>> -       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
>> +       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
>>          radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
>>                          S_370_WR_CONFIRM(1) |
>>                          S_370_ENGINE_SEL(V_370_PFP));
>> @@ -1493,7 +1493,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
>>
>>          assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
>>
>> -       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
>> +       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating));
>>          radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
>>                          S_370_WR_CONFIRM(1) |
>>                          S_370_ENGINE_SEL(V_370_PFP));
>> --
>> 2.21.0
>>
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