[Mesa-dev] [PATCH 07/10] panfrost/midgard/disasm: Support 8-bit destination

[Alyssa Rosenzweig]

Meanwhile, we're forced to disable dest_override, since it's not yet
clear how this interacts with other bitnesses (it'll likely need to be
overhauled in any case).

Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
---
 .../drivers/panfrost/midgard/disassemble.c    | 39 ++++++++++---------
 1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/disassemble.c b/src/gallium/drivers/panfrost/midgard/disassemble.c
index 4583e9e1584..71f5c489528 100644
--- a/src/gallium/drivers/panfrost/midgard/disassemble.c
+++ b/src/gallium/drivers/panfrost/midgard/disassemble.c
@@ -298,27 +298,30 @@ print_vector_field(const char *name, uint16_t *words, uint16_t reg_word,
 
         out_half = half;
 
-        if (alu_field->dest_override != midgard_dest_override_none) {
-                if (out_half)
-                        printf("/* half */ ");
+        /* First, print the destination */
+        {
+                int out_reg = reg_info->out_reg;
+                unsigned bits = 32;
 
-                out_half = true;
+                if (alu_field->dest_override != midgard_dest_override_none) {
+                        printf("/* do%d */ ", alu_field->dest_override);
+                }
 
-                if (alu_field->dest_override == midgard_dest_override_lower)
-                        out_high = false;
-                else if (alu_field->dest_override == midgard_dest_override_upper)
-                        out_high = true;
-                else
-                        assert(0);
-        }
+                if (alu_field->reg_mode == midgard_reg_mode_16) {
+                        bits = 16;
+                        out_reg *= 2;
+                        out_reg += out_high;
+                } else if (alu_field->reg_mode == midgard_reg_mode_8) {
+                        bits = 8;
+                        out_reg *= 4;
+                        out_reg += out_high;
+                } else if (alu_field->reg_mode == midgard_reg_mode_64) {
+                        bits = 64;
+                        /* TODO */
+                }
 
-        if (out_half) {
-                if (out_high)
-                        print_reg(2 * reg_info->out_reg + 1, 16);
-                else
-                        print_reg(2 * reg_info->out_reg, 16);
-        } else
-                print_reg(reg_info->out_reg, 32);
+                print_reg(out_reg, bits);
+        }
 
         if (mask != 0xF) {
                 unsigned i;
-- 
2.20.1