[Mesa-dev] [PATCH 02/13] panfrost/midgard: Share some utility functions
Alyssa Rosenzweig
alyssa at rosenzweig.io
Sun May 26 02:39:13 UTC 2019
These were static to midgard_compile.c but are more generally useful
across the compiler; move them to common Midgard code.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
---
.../drivers/panfrost/midgard/compiler.h | 46 ++++++++
.../drivers/panfrost/midgard/helpers.h | 50 +++++++++
.../panfrost/midgard/midgard_compile.c | 104 ------------------
.../drivers/panfrost/midgard/midgard_ops.h | 21 ++++
4 files changed, 117 insertions(+), 104 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/compiler.h b/src/gallium/drivers/panfrost/midgard/compiler.h
index 48c6db542a5..31fa0240fb8 100644
--- a/src/gallium/drivers/panfrost/midgard/compiler.h
+++ b/src/gallium/drivers/panfrost/midgard/compiler.h
@@ -348,6 +348,52 @@ void mir_print_instruction(midgard_instruction *ins);
void mir_print_block(midgard_block *block);
void mir_print_shader(compiler_context *ctx);
+/* MIR goodies */
+
+static const midgard_vector_alu_src blank_alu_src = {
+ .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
+};
+
+static const midgard_vector_alu_src blank_alu_src_xxxx = {
+ .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
+};
+
+static const midgard_scalar_alu_src blank_scalar_alu_src = {
+ .full = true
+};
+
+/* Used for encoding the unused source of 1-op instructions */
+static const midgard_vector_alu_src zero_alu_src = { 0 };
+
+/* 'Intrinsic' move for aliasing */
+
+static inline midgard_instruction
+v_fmov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
+{
+ midgard_instruction ins = {
+ .type = TAG_ALU_4,
+ .ssa_args = {
+ .src0 = SSA_UNUSED_1,
+ .src1 = src,
+ .dest = dest,
+ },
+ .alu = {
+ .op = midgard_alu_op_fmov,
+ .reg_mode = midgard_reg_mode_32,
+ .dest_override = midgard_dest_override_none,
+ .mask = 0xFF,
+ .src1 = vector_alu_srco_unsigned(zero_alu_src),
+ .src2 = vector_alu_srco_unsigned(mod)
+ },
+ };
+
+ return ins;
+}
+
+/* Scheduling */
+
+void schedule_program(compiler_context *ctx);
+
/* Register allocation */
struct ra_graph;
diff --git a/src/gallium/drivers/panfrost/midgard/helpers.h b/src/gallium/drivers/panfrost/midgard/helpers.h
index 9d287259a8a..cf3a63e7587 100644
--- a/src/gallium/drivers/panfrost/midgard/helpers.h
+++ b/src/gallium/drivers/panfrost/midgard/helpers.h
@@ -22,6 +22,8 @@
#ifndef __MDG_HELPERS_H
#define __MDG_HELPERS_H
+#include <string.h>
+
#define OP_IS_STORE_VARY(op) (\
op == midgard_op_st_vary_16 || \
op == midgard_op_st_vary_32 \
@@ -158,4 +160,52 @@ struct mir_op_props {
/* This file is common, so don't define the tables themselves. #include
* midgard_op.h if you need that, or edit midgard_ops.c directly */
+/* Duplicate bits to convert standard 4-bit writemask to duplicated 8-bit
+ * format (or do the inverse). The 8-bit format only really matters for
+ * int8, as far as I know, where performance can be improved by using a
+ * vec8 output */
+
+static inline unsigned
+expand_writemask(unsigned mask)
+{
+ unsigned o = 0;
+
+ for (int i = 0; i < 4; ++i)
+ if (mask & (1 << i))
+ o |= (3 << (2 * i));
+
+ return o;
+}
+
+static inline unsigned
+squeeze_writemask(unsigned mask)
+{
+ unsigned o = 0;
+
+ for (int i = 0; i < 4; ++i)
+ if (mask & (3 << (2 * i)))
+ o |= (1 << i);
+
+ return o;
+
+}
+
+/* Coerce structs to integer */
+
+static inline unsigned
+vector_alu_srco_unsigned(midgard_vector_alu_src src)
+{
+ unsigned u;
+ memcpy(&u, &src, sizeof(src));
+ return u;
+}
+
+static inline midgard_vector_alu_src
+vector_alu_from_unsigned(unsigned u)
+{
+ midgard_vector_alu_src s;
+ memcpy(&s, &u, sizeof(s));
+ return s;
+}
+
#endif
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index cd2029eb70b..ab1d259e0d4 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -107,39 +107,6 @@ midgard_block_add_successor(midgard_block *block, midgard_block *successor)
#define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
#define M_STORE(name) M_LOAD_STORE(name, src0, dest)
-const midgard_vector_alu_src blank_alu_src = {
- .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
-};
-
-const midgard_vector_alu_src blank_alu_src_xxxx = {
- .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
-};
-
-const midgard_scalar_alu_src blank_scalar_alu_src = {
- .full = true
-};
-
-/* Used for encoding the unused source of 1-op instructions */
-const midgard_vector_alu_src zero_alu_src = { 0 };
-
-/* Coerce structs to integer */
-
-static unsigned
-vector_alu_srco_unsigned(midgard_vector_alu_src src)
-{
- unsigned u;
- memcpy(&u, &src, sizeof(src));
- return u;
-}
-
-static midgard_vector_alu_src
-vector_alu_from_unsigned(unsigned u)
-{
- midgard_vector_alu_src s;
- memcpy(&s, &u, sizeof(s));
- return s;
-}
-
/* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
* the corresponding Midgard source */
@@ -168,31 +135,6 @@ vector_alu_modifiers(nir_alu_src *src, bool is_int)
return alu_src;
}
-/* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
-
-static midgard_instruction
-v_fmov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
-{
- midgard_instruction ins = {
- .type = TAG_ALU_4,
- .ssa_args = {
- .src0 = SSA_UNUSED_1,
- .src1 = src,
- .dest = dest,
- },
- .alu = {
- .op = midgard_alu_op_fmov,
- .reg_mode = midgard_reg_mode_32,
- .dest_override = midgard_dest_override_none,
- .mask = 0xFF,
- .src1 = vector_alu_srco_unsigned(zero_alu_src),
- .src2 = vector_alu_srco_unsigned(mod)
- },
- };
-
- return ins;
-}
-
/* load/store instructions have both 32-bit and 16-bit variants, depending on
* whether we are using vectors composed of highp or mediump. At the moment, we
* don't support half-floats -- this requires changes in other parts of the
@@ -531,52 +473,6 @@ emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
_mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v);
}
-/* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
- * do the inverse) */
-
-static unsigned
-expand_writemask(unsigned mask)
-{
- unsigned o = 0;
-
- for (int i = 0; i < 4; ++i)
- if (mask & (1 << i))
- o |= (3 << (2 * i));
-
- return o;
-}
-
-static unsigned
-squeeze_writemask(unsigned mask)
-{
- unsigned o = 0;
-
- for (int i = 0; i < 4; ++i)
- if (mask & (3 << (2 * i)))
- o |= (1 << i);
-
- return o;
-
-}
-
-/* Determines effective writemask, taking quirks and expansion into account */
-static unsigned
-effective_writemask(midgard_vector_alu *alu)
-{
- /* Channel count is off-by-one to fit in two-bits (0 channel makes no
- * sense) */
-
- unsigned channel_count = GET_CHANNEL_COUNT(alu_opcode_props[alu->op].props);
-
- /* If there is a fixed channel count, construct the appropriate mask */
-
- if (channel_count)
- return (1 << channel_count) - 1;
-
- /* Otherwise, just squeeze the existing mask */
- return squeeze_writemask(alu->mask);
-}
-
static unsigned
nir_src_index(compiler_context *ctx, nir_src *src)
{
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ops.h b/src/gallium/drivers/panfrost/midgard/midgard_ops.h
index 8b363529aa9..78b999a8dc6 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_ops.h
+++ b/src/gallium/drivers/panfrost/midgard/midgard_ops.h
@@ -51,3 +51,24 @@ midgard_is_integer_out_op(int op)
return is_int ^ is_conversion;
}
+
+/* Determines effective writemask, taking quirks and expansion into account */
+static inline unsigned
+effective_writemask(midgard_vector_alu *alu)
+{
+ /* Channel count is off-by-one to fit in two-bits (0 channel makes no
+ * sense) */
+
+ unsigned channel_count = GET_CHANNEL_COUNT(alu_opcode_props[alu->op].props);
+
+ /* If there is a fixed channel count, construct the appropriate mask */
+
+ if (channel_count)
+ return (1 << channel_count) - 1;
+
+ /* Otherwise, just squeeze the existing mask */
+ return squeeze_writemask(alu->mask);
+}
+
+
+
--
2.20.1
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