[Mesa-dev] [PATCH 07/13] panfrost/midgard: Misc. cleanup for readibility
Alyssa Rosenzweig
alyssa at rosenzweig.io
Sun May 26 02:39:18 UTC 2019
Mostly, this fixes a number of instances of lines >> 80 chars,
refactoring them into something legible.
Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
---
.../drivers/panfrost/midgard/compiler.h | 38 +++++++++++----
.../panfrost/midgard/midgard_compile.c | 12 ++---
.../drivers/panfrost/midgard/midgard_ra.c | 46 ++++++++++++-------
3 files changed, 65 insertions(+), 31 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/compiler.h b/src/gallium/drivers/panfrost/midgard/compiler.h
index 31fa0240fb8..d3d64d37c49 100644
--- a/src/gallium/drivers/panfrost/midgard/compiler.h
+++ b/src/gallium/drivers/panfrost/midgard/compiler.h
@@ -313,17 +313,37 @@ mir_next_op(struct midgard_instruction *ins)
return list_first_entry(&(ins->link), midgard_instruction, link);
}
-#define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
-#define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
+#define mir_foreach_block(ctx, v) \
+ list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
-#define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
-#define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
-#define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
-#define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
-#define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
-#define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
-#define mir_foreach_instr_in_block_from_rev(block, v, from) list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
+#define mir_foreach_block_from(ctx, from, v) \
+ list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
+/* The following routines are for use before the scheduler has run */
+
+#define mir_foreach_instr(ctx, v) \
+ list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
+
+#define mir_foreach_instr_safe(ctx, v) \
+ list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
+
+#define mir_foreach_instr_in_block(block, v) \
+ list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
+
+#define mir_foreach_instr_in_block_safe(block, v) \
+ list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
+
+#define mir_foreach_instr_in_block_safe_rev(block, v) \
+ list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
+
+#define mir_foreach_instr_in_block_from(block, v, from) \
+ list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
+
+#define mir_foreach_instr_in_block_from_rev(block, v, from) \
+ list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
+
+#define mir_foreach_bundle_in_block(block, v) \
+ util_dynarray_foreach(&block->bundles, midgard_bundle, v)
static inline midgard_instruction *
mir_last_in_block(struct midgard_block *block)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 1c50a167097..4579a74f06c 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1726,8 +1726,10 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction
int op = ains->alu.op;
int units = alu_opcode_props[op].props;
- /* TODO: Promotion of scalars to vectors */
- int vector = ((!is_single_component_mask(ains->alu.mask)) || ((units & UNITS_SCALAR) == 0)) && (units & UNITS_ANY_VECTOR);
+ bool vectorable = units & UNITS_ANY_VECTOR;
+ bool scalarable = units & UNITS_SCALAR;
+ bool could_scalar = is_single_component_mask(ains->alu.mask);
+ bool vector = vectorable && !(could_scalar && scalarable);
if (!vector)
assert(units & UNITS_SCALAR);
@@ -1873,11 +1875,9 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction
}
- /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
- if (register_dep_mask & written_mask) {
- DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask, written_mask, register_dep_mask & written_mask);
+ /* Register dependencies of r0 must be out of fragment writeout bundle */
+ if (register_dep_mask & written_mask)
break;
- }
if (written_late)
break;
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ra.c b/src/gallium/drivers/panfrost/midgard/midgard_ra.c
index 7aa2932b806..c9a6c6e4710 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_ra.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_ra.c
@@ -88,7 +88,8 @@ compose_writemask(unsigned mask, struct phys_reg reg)
}
static unsigned
-compose_swizzle(unsigned swizzle, unsigned mask, struct phys_reg reg, struct phys_reg dst)
+compose_swizzle(unsigned swizzle, unsigned mask,
+ struct phys_reg reg, struct phys_reg dst)
{
unsigned out = 0;
@@ -127,7 +128,8 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash)
if ((hash < 0) || (hash >= SSA_FIXED_MINIMUM))
return hash;
- unsigned temp = (uintptr_t) _mesa_hash_table_u64_search(ctx->hash_to_temp, hash + 1);
+ unsigned temp = (uintptr_t) _mesa_hash_table_u64_search(
+ ctx->hash_to_temp, hash + 1);
if (temp)
return temp - 1;
@@ -136,7 +138,8 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash)
temp = ctx->temp_count++;
ctx->max_hash = MAX2(ctx->max_hash, hash);
- _mesa_hash_table_u64_insert(ctx->hash_to_temp, hash + 1, (void *) ((uintptr_t) temp + 1));
+ _mesa_hash_table_u64_insert(ctx->hash_to_temp,
+ hash + 1, (void *) ((uintptr_t) temp + 1));
return temp;
}
@@ -146,7 +149,7 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash)
static unsigned int
midgard_ra_select_callback(struct ra_graph *g, BITSET_WORD *regs, void *data)
{
- /* Choose the first available register to minimise reported register pressure */
+ /* Choose the first available register to minimise register pressure */
for (int i = 0; i < (16 * WORK_STRIDE); ++i) {
if (BITSET_TEST(regs, i)) {
@@ -231,7 +234,7 @@ allocate_registers(compiler_context *ctx)
};
/* Add the full set of work registers */
- for (int i = 0; i < work_count; ++i) {
+ for (unsigned i = 0; i < work_count; ++i) {
int base = WORK_STRIDE * i;
/* Build a full set of subdivisions */
@@ -246,13 +249,15 @@ allocate_registers(compiler_context *ctx)
ra_class_add_reg(regs, work_vec1, base + 8);
ra_class_add_reg(regs, work_vec1, base + 9);
- for (unsigned i = 0; i < 10; ++i) {
- for (unsigned j = 0; j < 10; ++j) {
- unsigned mask1 = reg_type_to_mask[i];
- unsigned mask2 = reg_type_to_mask[j];
+ for (unsigned a = 0; a < 10; ++a) {
+ unsigned mask1 = reg_type_to_mask[a];
+
+ for (unsigned b = 0; b < 10; ++b) {
+ unsigned mask2 = reg_type_to_mask[b];
if (mask1 & mask2)
- ra_add_reg_conflict(regs, base + i, base + j);
+ ra_add_reg_conflict(regs,
+ base + a, base + b);
}
}
}
@@ -344,7 +349,8 @@ allocate_registers(compiler_context *ctx)
if (ins->ssa_args.dest < 0) continue;
if (ins->ssa_args.dest < SSA_FIXED_MINIMUM) {
- /* If this destination is not yet live, it is now since we just wrote it */
+ /* If this destination is not yet live, it is
+ * now since we just wrote it */
int dest = ins->ssa_args.dest;
@@ -357,7 +363,9 @@ allocate_registers(compiler_context *ctx)
* invocations, and if there are none, the source dies
* */
- int sources[2] = { ins->ssa_args.src0, ins->ssa_args.src1 };
+ int sources[2] = {
+ ins->ssa_args.src0, ins->ssa_args.src1
+ };
for (int src = 0; src < 2; ++src) {
int s = sources[src];
@@ -388,7 +396,10 @@ allocate_registers(compiler_context *ctx)
for (int i = 0; i < nodes; ++i) {
for (int j = i + 1; j < nodes; ++j) {
- if (!(live_start[i] >= live_end[j] || live_start[j] >= live_end[i]))
+ bool j_overlaps_i = live_start[j] < live_end[i];
+ bool i_overlaps_j = live_end[j] < live_start[i];
+
+ if (i_overlaps_j || j_overlaps_i)
ra_add_node_interference(g, i, j);
}
}
@@ -442,18 +453,21 @@ install_registers_instr(
ins->registers.src2_imm = args.inline_constant;
if (args.inline_constant) {
- /* Encode inline 16-bit constant as a vector by default */
+ /* Encode inline 16-bit constant. See disassembler for
+ * where the algorithm is from */
ins->registers.src2_reg = ins->inline_constant >> 11;
int lower_11 = ins->inline_constant & ((1 << 12) - 1);
+ uint16_t imm = ((lower_11 >> 8) & 0x7) |
+ ((lower_11 & 0xFF) << 3);
- uint16_t imm = ((lower_11 >> 8) & 0x7) | ((lower_11 & 0xFF) << 3);
ins->alu.src2 = imm << 2;
} else {
midgard_vector_alu_src mod2 =
vector_alu_from_unsigned(ins->alu.src2);
- mod2.swizzle = compose_swizzle(mod2.swizzle, mask, src2, dest);
+ mod2.swizzle = compose_swizzle(
+ mod2.swizzle, mask, src2, dest);
ins->alu.src2 = vector_alu_srco_unsigned(mod2);
ins->registers.src2_reg = src2.reg;
--
2.20.1
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