[Mesa-dev] [PATCH 12/13] panfrost/midgard: Remove r0 scheduling code

[Alyssa Rosenzweig]

This code needs to be rewritten to be RA-agnostic, but until register
pinning is setup the right way for fragment output it's broken dead
code; remove it.

Signed-off-by: Alyssa Rosenzweig <alyssa at rosenzweig.io>
---
 .../panfrost/midgard/midgard_schedule.c       | 82 +++----------------
 1 file changed, 12 insertions(+), 70 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
index 1a562af8142..b65f6ee6eb3 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
@@ -287,76 +287,18 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction
                                 /* All of r0 has to be written out along with
                                  * the branch writeout */
 
-                                if (ains->writeout) {
-                                        if (index == 0) {
-                                                /* Inject a move */
-                                                midgard_instruction ins = v_fmov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
-                                                ins.unit = UNIT_VMUL;
-                                                control |= ins.unit;
-
-                                                /* TODO don't leak */
-                                                midgard_instruction *move =
-                                                        mem_dup(&ins, sizeof(midgard_instruction));
-                                                bytes_emitted += sizeof(midgard_reg_info);
-                                                bytes_emitted += sizeof(midgard_vector_alu);
-                                                bundle.instructions[packed_idx++] = move;
-                                        } else {
-                                                /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies */
-                                                bool written_late = false;
-                                                bool components[4] = { 0 };
-                                                uint16_t register_dep_mask = 0;
-                                                uint16_t written_mask = 0;
-
-                                                midgard_instruction *qins = ins;
-                                                for (int t = 0; t < index; ++t) {
-                                                        if (qins->registers.out_reg != 0) {
-                                                                /* Mark down writes */
-
-                                                                written_mask |= (1 << qins->registers.out_reg);
-                                                        } else {
-                                                                /* Mark down the register dependencies for errata check */
-
-                                                                if (qins->registers.src1_reg < 16)
-                                                                        register_dep_mask |= (1 << qins->registers.src1_reg);
-
-                                                                if (qins->registers.src2_reg < 16)
-                                                                        register_dep_mask |= (1 << qins->registers.src2_reg);
-
-                                                                int mask = qins->alu.mask;
-
-                                                                for (int c = 0; c < 4; ++c)
-                                                                        if (mask & (0x3 << (2 * c)))
-                                                                                components[c] = true;
-
-                                                                /* ..but if the writeout is too late, we have to break up anyway... for some reason */
-
-                                                                if (qins->unit == UNIT_VLUT)
-                                                                        written_late = true;
-                                                        }
-
-                                                        /* Advance instruction pointer */
-                                                        qins = mir_next_op(qins);
-                                                }
-
-                                                /* Register dependencies of r0 must be out of fragment writeout bundle */
-                                                if (register_dep_mask & written_mask)
-                                                        break;
-
-                                                if (written_late)
-                                                        break;
-
-                                                /* If even a single component is not written, break it up (conservative check). */
-                                                bool breakup = false;
-
-                                                for (int c = 0; c < 4; ++c)
-                                                        if (!components[c])
-                                                                breakup = true;
-
-                                                if (breakup)
-                                                        break;
-
-                                                /* Otherwise, we're free to proceed */
-                                        }
+                                if (ains->writeout && index == 0) {
+                                        /* Inject a move */
+                                        midgard_instruction ins = v_fmov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
+                                        ins.unit = UNIT_VMUL;
+                                        control |= ins.unit;
+
+                                        /* TODO don't leak */
+                                        midgard_instruction *move =
+                                                mem_dup(&ins, sizeof(midgard_instruction));
+                                        bytes_emitted += sizeof(midgard_reg_info);
+                                        bytes_emitted += sizeof(midgard_vector_alu);
+                                        bundle.instructions[packed_idx++] = move;
                                 }
 
                                 if (ains->unit == ALU_ENAB_BRANCH) {
-- 
2.20.1