[Mesa-dev] [PATCH 5/7] radv: decompress HTILE if the resolve src image is compressed

[Bas Nieuwenhuizen]

On Mon, May 27, 2019 at 5:38 PM Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
>
> It's required to decompress HTILE before resolving with the
> compute path.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/amd/vulkan/radv_meta_resolve.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
> index 2d048207b7a..8891a98e4d7 100644
> --- a/src/amd/vulkan/radv_meta_resolve.c
> +++ b/src/amd/vulkan/radv_meta_resolve.c
> @@ -769,6 +769,32 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer)
>                 radv_decompress_resolve_src(cmd_buffer, src_image,
>                                             src_att.layout, 1, &region);
>         }
> +
> +       if (subpass->ds_resolve_attachment) {
> +               struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
> +               struct radv_image *src_image =
> +                       fb->attachments[src_att.attachment].attachment->image;
> +               uint32_t queue_mask =
> +                       radv_image_queue_family_mask(src_image,
> +                                                    cmd_buffer->queue_family_index,
> +                                                    cmd_buffer->queue_family_index);
> +
> +               VkImageSubresourceRange range;
> +               range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
> +               range.baseMipLevel = 0;
> +               range.levelCount = 1;
> +               range.baseArrayLayer = 0;
> +               range.layerCount = src_image->info.array_size;

Shouldn't we take this from the image view + layers in the framebuffer?

> +
> +               if (radv_layout_is_htile_compressed(src_image, src_att.layout,
> +                                                   queue_mask)) {
> +                       radv_decompress_depth_image_inplace(cmd_buffer, src_image,
> +                                                           &range);
> +
> +                       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
> +                                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
> +               }
Can't we do a proper layout transition? That should deal automatically
with tc compatible HTILE, and avoid open-coding this.
> +       }
>  }
>
>  /**
> --
> 2.21.0
>
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