[Mesa-dev] [PATCH v3 03/18] intel/blorp: Use the hardware op for CCS ambiguate on gen10+

[Nanley Chery]

Thanks. Landed.

On Thu, May 30, 2019 at 7:02 AM Jason Ekstrand <jason at jlekstrand.net> wrote:
>
> Feel free to land
>
> On Wed, May 29, 2019 at 4:50 PM Nanley Chery <nanleychery at gmail.com> wrote:
>>
>> On Wed, Feb 14, 2018 at 12:19 PM Jason Ekstrand <jason at jlekstrand.net> wrote:
>> >
>> > Cannonlake hardware adds a new resolve type in 3DSTATE_PS called
>> > FAST_CLEAR_0 which does an ambiguate.  Now that the hardware can do it
>> > directly, we should use that instead of binding the CCS as a render
>> > target and doing it manually.  This was tested with a full Vulkan CTS
>> > run on Cannonlake.
>> > ---
>> >  src/intel/blorp/blorp_clear.c     | 12 +++++++++++-
>> >  src/intel/blorp/blorp_genX_exec.h |  6 ++++++
>> >  2 files changed, 17 insertions(+), 1 deletion(-)
>> >
>>
>> This patch is
>> Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
>>
>> > diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
>> > index 421a6c5..4ba65d0 100644
>> > --- a/src/intel/blorp/blorp_clear.c
>> > +++ b/src/intel/blorp/blorp_clear.c
>> > @@ -758,7 +758,11 @@ blorp_ccs_resolve(struct blorp_batch *batch,
>> >     params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown;
>> >     params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
>> >
>> > -   if (batch->blorp->isl_dev->info->gen >= 9) {
>> > +   if (batch->blorp->isl_dev->info->gen >= 10) {
>> > +      assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
>> > +             resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE ||
>> > +             resolve_op == ISL_AUX_OP_AMBIGUATE);
>> > +   } else if (batch->blorp->isl_dev->info->gen >= 9) {
>> >        assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
>> >               resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
>> >     } else {
>> > @@ -893,6 +897,12 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
>> >                      struct blorp_surf *surf,
>> >                      uint32_t level, uint32_t layer)
>> >  {
>> > +   if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) {
>> > +      /* On gen10 and above, we have a hardware resolve op for this */
>> > +      return blorp_ccs_resolve(batch, surf, level, layer, 1,
>> > +                               surf->surf->format, ISL_AUX_OP_AMBIGUATE);
>> > +   }
>> > +
>> >     struct blorp_params params;
>> >     blorp_params_init(&params);
>> >
>> > diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
>> > index 5e1312a..85abf6b 100644
>> > --- a/src/intel/blorp/blorp_genX_exec.h
>> > +++ b/src/intel/blorp/blorp_genX_exec.h
>> > @@ -752,6 +752,12 @@ blorp_emit_ps_config(struct blorp_batch *batch,
>> >        switch (params->fast_clear_op) {
>> >        case ISL_AUX_OP_NONE:
>> >           break;
>> > +#if GEN_GEN >= 10
>> > +      case ISL_AUX_OP_AMBIGUATE:
>> > +         ps.RenderTargetFastClearEnable = true;
>> > +         ps.RenderTargetResolveType = FAST_CLEAR_0;
>> > +         break;
>> > +#endif
>> >  #if GEN_GEN >= 9
>> >        case ISL_AUX_OP_PARTIAL_RESOLVE:
>> >           ps.RenderTargetResolveType = RESOLVE_PARTIAL;
>> > --
>> > 2.5.0.400.gff86faf
>> >
>> > _______________________________________________
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>> > mesa-dev at lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev