commit b3b2f97f2e breaks Civilization VI and wine on gfx10

[Bert Karwatzki]

When using an either Civilization VI or MTGA (Magic The Gathering Arena) with
wine on the gfx10 card of my Msi alpha 15 laptop I quickly get crashes and the
following errors in dmesg (on the gfx9 everything works, vulkan application
also work on the gfx10 so it's unlikely it's a hardware problem):

GPUs:
03:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI] Navi 23 [Radeon RX 6600/6600 XT/6600M] (rev c3)
08:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Cezanne [Radeon Vega Series / Radeon Vega Mobile Series] (rev c5)

Error:
[14743.562243] [  T16788] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx_0.0.0 timeout, signaled seq=646241, emitted seq=646243
[14743.562358] [  T16788] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process information: process Civ6 pid 27986 thread Civ6:cs0 pid 27993
[14743.562446] [  T16788] amdgpu 0000:03:00.0: amdgpu: GPU reset begin!
[14743.664240] [  T16788] amdgpu 0000:03:00.0: amdgpu: MODE1 reset
[14743.664247] [  T16788] amdgpu 0000:03:00.0: amdgpu: GPU mode1 reset
[14743.664322] [  T16788] amdgpu 0000:03:00.0: amdgpu: GPU smu mode1 reset
[14744.168380] [  T16788] amdgpu 0000:03:00.0: amdgpu: GPU reset succeeded, trying to resume
[14744.168562] [  T16788] [drm] PCIE GART of 512M enabled (table at 0x00000081FEB00000).
[14744.168657] [  T16788] [drm] VRAM is lost due to GPU reset!
[...]
[14744.530114] [  T16788] amdgpu 0000:03:00.0: amdgpu: GPU reset(6) succeeded!
[14744.530220] [  T27993] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to initialize parser -125!

This affects every mesa version since 22.0.0, the last mesa version on not affected
is 21.3.8. Using the Civ6 "Gathering the Storm AI benchmark" (the most demanding of Civ6
builtin bencharks) I bisected this to commit b3b2f97f2e25 ("radeonsi: add Wave32 heuristics
and shader profiles"). This commit does not revert cleanly in mesa-22.0.0, but simply setting

unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *shader)
{
   /* There are a few uses that pass shader=NULL here, expecting the default compute wave size. */
   struct si_shader_info *info = shader ? &shader->selector->info : NULL;
   gl_shader_stage stage = info ? info->stage : MESA_SHADER_COMPUTE;

   return 64;
}

resolves the issue for me. Next I'm going to try to pinpoint which of the "return 32;"
statements in si_determine_wave_size() actually cause the bug so some optimizations can
be kept.

Link: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11866

Bert Karwatzki