<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Apr 7, 2016 at 2:37 PM, Matt Turner <span dir="ltr"><<a href="mailto:mattst88@gmail.com" target="_blank">mattst88@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On Wed, Dec 9, 2015 at 8:23 PM, Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>> wrote:<br>
> While we're at it, we also add support for the possibility that the<br>
> indirect is, in fact, a constant. This shouldn't happen in the common case<br>
> (if it does, that means NIR failed to constant-fold something), but it's<br>
> possible so we should handle it.<br>
> ---<br>
> src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++<br>
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 51 +++++++++++++++++++-------<br>
> 2 files changed, 42 insertions(+), 13 deletions(-)<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp<br>
> index 9eaf8d0..a2ec03e 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp<br>
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp<br>
> @@ -4424,6 +4424,10 @@ get_lowered_simd_width(const struct brw_device_info *devinfo,<br>
> case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:<br>
> return 8;<br>
><br>
> + case SHADER_OPCODE_MOV_INDIRECT:<br>
> + /* Prior to Broadwell, we only have 8 address subregisters */<br>
> + return devinfo->gen < 8 ? 8 : inst->exec_size;<br>
<br>
</span>There are still only 16 on BDW+, would it make sense to change the<br>
last expression to MIN2(inst->exec_size, 16)?<br></blockquote><div><br></div><div>For the sake of Curro and his SIMD32 efforts, yes. Either that or he can catch it in the rebase. I don't care.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div><div class="h5"><br>
> +<br>
> default:<br>
> return inst->exec_size;<br>
> }<br>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp<br>
> index d86eee1..7fa6d84 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp<br>
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp<br>
> @@ -351,22 +351,47 @@ fs_generator::generate_mov_indirect(fs_inst *inst,<br>
><br>
> unsigned imm_byte_offset = <a href="http://reg.nr" rel="noreferrer" target="_blank">reg.nr</a> * REG_SIZE + reg.subnr;<br>
><br>
> - /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */<br>
> - struct brw_reg addr = vec8(brw_address_reg(0));<br>
> + if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {<br>
> + imm_byte_offset += indirect_byte_offset.ud;<br>
><br>
> - /* The destination stride of an instruction (in bytes) must be greater<br>
> - * than or equal to the size of the rest of the instruction. Since the<br>
> - * address register is of type UW, we can't use a D-type instruction.<br>
> - * In order to get around this, re re-type to UW and use a stride.<br>
> - */<br>
> - indirect_byte_offset =<br>
> - retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);<br>
> + <a href="http://reg.nr" rel="noreferrer" target="_blank">reg.nr</a> = imm_byte_offset / REG_SIZE;<br>
> + reg.subnr = imm_byte_offset % REG_SIZE;<br>
> + brw_MOV(p, dst, reg);<br>
> + } else {<br>
> + /* Prior to Broadwell, there are only 8 address registers. */<br>
> + assert(inst->exec_size == 8 || devinfo->gen >= 8);<br>
><br>
> - /* Prior to Broadwell, there are only 8 address registers. */<br>
> - assert(inst->exec_size == 8 || devinfo->gen >= 8);<br>
> + /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */<br>
> + struct brw_reg addr = vec8(brw_address_reg(0));<br>
><br>
> - brw_MOV(p, addr, indirect_byte_offset);<br>
> - brw_MOV(p, dst, retype(brw_VxH_indirect(0, imm_byte_offset), dst.type));<br>
> + /* The destination stride of an instruction (in bytes) must be greater<br>
> + * than or equal to the size of the rest of the instruction. Since the<br>
> + * address register is of type UW, we can't use a D-type instruction.<br>
> + * In order to get around this, re re-type to UW and use a stride.<br>
<br>
</div></div>s/re re-type/retype/ while we're moving it.<br><div><div class="h5"></div></div></blockquote><div><br></div><div>Sure<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div class="h5">
> + */<br>
> + indirect_byte_offset =<br>
> + retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);<br>
> +<br>
> + if (devinfo->gen < 8) {<br>
> + /* Prior to broadwell, we have a restriction that the bottom 5 bits<br>
> + * of the base offset and the bottom 5 bits of the indirect must add<br>
> + * to less than 32. In other words, the hardware needs to be able to<br>
> + * add the bottom five bits of the two to get the subnumber and add<br>
> + * the next 7 bits of each to get the actual register number. Since<br>
> + * the indirect may cause us to cross a register boundary, this makes<br>
> + * it almost useless. We could try and do something clever where we<br>
> + * use a actual base offset if base_offset % 32 == 0 but that would<br>
> + * mean we were generating different code depending on the base<br>
> + * offset. Instead, for the sake of consistency, we'll just do the<br>
> + * add ourselves.<br>
> + */<br>
> + brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));<br>
> + brw_MOV(p, dst, retype(brw_VxH_indirect(0, 0), dst.type));<br>
> + } else {<br>
> + brw_MOV(p, addr, indirect_byte_offset);<br>
> + brw_MOV(p, dst, retype(brw_VxH_indirect(0, imm_byte_offset), dst.type));<br>
> + }<br>
> + }<br>
> }<br>
><br>
> void<br>
> --<br>
> 2.5.0.400.gff86faf<br>
><br>
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</blockquote></div><br></div></div>