On Apr 23, 2016 4:39 PM, "Kenneth Graunke" <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>> wrote: > > From: Jason Ekstrand <<a href="mailto:jason.ekstrand@intel.com">jason.ekstrand@intel.com</a>> > > Reviewed-by: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>> > --- > src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 +++++++- > src/mesa/drivers/dri/i965/brw_shader.cpp | 3 ++- > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > index 725f5da..43d3745 100644 > --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > @@ -3205,12 +3205,18 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) > case nir_texop_txs: op = ir_txs; break; > case nir_texop_texture_samples: { > fs_reg dst = retype(get_nir_dest(instr->dest), BRW_REGISTER_TYPE_D); > - fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, dst, > + > + fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D, 4); This one should Cc stable. The previous behavior would only allocate one register and then write four thus potentially stomping three innocent bystanders. I've never seen an actual bug related to it but sampleinfo is newish. > + fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, tmp, > bld.vgrf(BRW_REGISTER_TYPE_D, 1), > texture_reg, texture_reg); > inst->mlen = 1; > inst->header_size = 1; > inst->base_mrf = -1; > + inst->regs_written = 4 * (dispatch_width / 8); > + > + /* Pick off the one component we care about */ > + bld.MOV(dst, tmp); > return; > } > case nir_texop_samples_identical: op = ir_samples_identical; break; > diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp > index 376cb25..76c4a52 100644 > --- a/src/mesa/drivers/dri/i965/brw_shader.cpp > +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp > @@ -710,7 +710,8 @@ backend_instruction::is_tex() const > opcode == SHADER_OPCODE_TXS || > opcode == SHADER_OPCODE_LOD || > opcode == SHADER_OPCODE_TG4 || > - opcode == SHADER_OPCODE_TG4_OFFSET); > + opcode == SHADER_OPCODE_TG4_OFFSET || > + opcode == SHADER_OPCODE_SAMPLEINFO); > } > > bool > -- > 2.8.0 > > _______________________________________________ > mesa-dev mailing list > <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> > <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a>