<div dir="ltr"><div>I sent a few fairly minor comments that I'd like to see addressed. Other than those, </div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>> </div><div class="gmail_extra"> <div class="gmail_quote">On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez <<a href="mailto:currojerez@riseup.net" target="_blank">currojerez@riseup.net</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">This should be enough to get the FS generator emitting 32-wide code for at least compute shaders. Most of the work in this series is about fixing the current codegen infrastructure to support arbitrary channel group controls and execution sizes (other than dispatch_width that is), and extending several virtual opcodes to handle SIMD32 (only the changes for opcodes that can potentially be used in compute shaders are included here). Enjoy. [PATCH 01/21] i965/eu: Define alternative interface for setting compression and group controls. [PATCH 02/21] i965/eu: Fix a bunch of compression control bugs in the generator. [PATCH 03/21] i965/fs: No need to set compression control at the top of generate_code(). [PATCH 04/21] i965/fs: Simplify per-instruction compression control setup in generator. [PATCH 05/21] i965/fs: Pass the compression mode to brw_reg_from_fs_reg(). [PATCH 06/21] i965/fs: Extend region width calculation to allow arbitrary execution sizes. [PATCH 07/21] i965/eu: Stop using p->compressed to specify the exec size of control flow instructions. [PATCH 08/21] i965/fs: Pass current execution size to brw_IF() and brw_DO(). [PATCH 09/21] i965/fs: No need to reset predicate control after emitting some instructions. [PATCH 10/21] i965/eu: Use current exec size instead of p->compressed in surface message generation. [PATCH 11/21] i965/eu: Remove brw_codegen::compressed and ::compressed_stack. [PATCH 12/21] i965/fs: Clean up remaining uses of dispatch_width in the generator. [PATCH 13/21] i965/eu: Consider QtrCtrl 3Q-4Q in typed surface message descriptor setup. [PATCH 14/21] i965/eu: Set execution size explicitly for memory fence send message. [PATCH 15/21] i965/eu: Fix Gen7+ DP scratch message size calculation on Gen7. [PATCH 16/21] i965/fs: Implement scratch reads and writes of 4 GRFs at a time. [PATCH 17/21] i965/fs: Lower 32-wide scratch writes in the generator. [PATCH 18/21] i965/fs: Allow specifying arbitrary execution sizes up to 32 to FIND_LIVE_CHANNEL. [PATCH 19/21] i965/fs: Allow specifying arbitrary quarter control to FIND_LIVE_CHANNEL. [PATCH 20/21] i965/ir: Make BROADCAST emit an unmasked single-channel move. [PATCH 21/21] i965/fs: Expose arbitrary channel execution groups to the IR. _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div>