<p dir="ltr">Thanks for fixing this! Rb</p>
<div class="gmail_quote">On May 28, 2016 23:02, "Jordan Justen" <<a href="mailto:jordan.l.justen@intel.com">jordan.l.justen@intel.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">It appears we were over-allocating these arrays.<br>
<br>
Previously we would use nir->num_uniforms directly for scalar<br>
programs, and multiply it by 4 for vec4 programs.<br>
<br>
Instead we should have been dividing by 4 in both cases to convert<br>
from bytes to a gl_constant_value count. The size of gl_constant_value<br>
is 4 bytes.<br>
<br>
Signed-off-by: Jordan Justen <<a href="mailto:jordan.l.justen@intel.com">jordan.l.justen@intel.com</a>><br>
---<br>
Jenkins results looked good with this change.<br>
<br>
src/mesa/drivers/dri/i965/brw_cs.c | 2 +-<br>
src/mesa/drivers/dri/i965/brw_gs.c | 4 +---<br>
src/mesa/drivers/dri/i965/brw_tcs.c | 4 +---<br>
src/mesa/drivers/dri/i965/brw_tes.c | 4 +---<br>
src/mesa/drivers/dri/i965/brw_vs.c | 4 +---<br>
src/mesa/drivers/dri/i965/brw_wm.c | 2 +-<br>
6 files changed, 6 insertions(+), 14 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c<br>
index 0ab9ebd..a9cbde9 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_cs.c<br>
+++ b/src/mesa/drivers/dri/i965/brw_cs.c<br>
@@ -91,7 +91,7 @@ brw_codegen_cs_prog(struct brw_context *brw,<br>
* prog_data associated with the compiled program, and which will be freed<br>
* by the state cache.<br>
*/<br>
- int param_count = cp->program.Base.nir->num_uniforms;<br>
+ int param_count = cp->program.Base.nir->num_uniforms / 4;<br>
<br>
/* The backend also sometimes adds params for texture size. */<br>
param_count += 2 * ctx->Const.Program[MESA_SHADER_COMPUTE].MaxTextureImageUnits;<br>
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c<br>
index 8f5dcf3..7ead182 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_gs.c<br>
+++ b/src/mesa/drivers/dri/i965/brw_gs.c<br>
@@ -119,9 +119,7 @@ brw_codegen_gs_prog(struct brw_context *brw,<br>
*/<br>
struct gl_shader *gs = prog->_LinkedShaders[MESA_SHADER_GEOMETRY];<br>
struct brw_shader *bgs = (struct brw_shader *) gs;<br>
- int param_count = gp->program.Base.nir->num_uniforms;<br>
- if (!compiler->scalar_stage[MESA_SHADER_GEOMETRY])<br>
- param_count *= 4;<br>
+ int param_count = gp->program.Base.nir->num_uniforms / 4;<br>
<br>
prog_data.base.base.param =<br>
rzalloc_array(NULL, const gl_constant_value *, param_count);<br>
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c<br>
index 9589fa5..5a514ef 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_tcs.c<br>
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c<br>
@@ -199,9 +199,7 @@ brw_codegen_tcs_prog(struct brw_context *brw,<br>
*/<br>
struct gl_shader *tcs = shader_prog ?<br>
shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] : NULL;<br>
- int param_count = nir->num_uniforms;<br>
- if (!compiler->scalar_stage[MESA_SHADER_TESS_CTRL])<br>
- param_count *= 4;<br>
+ int param_count = nir->num_uniforms / 4;<br>
<br>
prog_data.base.base.param =<br>
rzalloc_array(NULL, const gl_constant_value *, param_count);<br>
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c<br>
index b7f1677..a4cd4da 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_tes.c<br>
+++ b/src/mesa/drivers/dri/i965/brw_tes.c<br>
@@ -151,9 +151,7 @@ brw_codegen_tes_prog(struct brw_context *brw,<br>
* every uniform is a float which gets padded to the size of a vec4.<br>
*/<br>
struct gl_shader *tes = shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];<br>
- int param_count = nir->num_uniforms;<br>
- if (!compiler->scalar_stage[MESA_SHADER_TESS_EVAL])<br>
- param_count *= 4;<br>
+ int param_count = nir->num_uniforms / 4;<br>
<br>
prog_data.base.base.param =<br>
rzalloc_array(NULL, const gl_constant_value *, param_count);<br>
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c<br>
index 2478e62..abf03b1 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_vs.c<br>
+++ b/src/mesa/drivers/dri/i965/brw_vs.c<br>
@@ -80,9 +80,7 @@ brw_codegen_vs_prog(struct brw_context *brw,<br>
* prog_data associated with the compiled program, and which will be freed<br>
* by the state cache.<br>
*/<br>
- int param_count = vp->program.Base.nir->num_uniforms;<br>
- if (!compiler->scalar_stage[MESA_SHADER_VERTEX])<br>
- param_count *= 4;<br>
+ int param_count = vp->program.Base.nir->num_uniforms / 4;<br>
<br>
if (vs)<br>
prog_data.base.base.nr_image_params = vs->base.NumImages;<br>
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c<br>
index 1943d08..c9c5d5e 100644<br>
--- a/src/mesa/drivers/dri/i965/brw_wm.c<br>
+++ b/src/mesa/drivers/dri/i965/brw_wm.c<br>
@@ -97,7 +97,7 @@ brw_codegen_wm_prog(struct brw_context *brw,<br>
* prog_data associated with the compiled program, and which will be freed<br>
* by the state cache.<br>
*/<br>
- int param_count = fp->program.Base.nir->num_uniforms;<br>
+ int param_count = fp->program.Base.nir->num_uniforms / 4;<br>
if (fs)<br>
prog_data.base.nr_image_params = fs->base.NumImages;<br>
/* The backend also sometimes adds params for texture size. */<br>
--<br>
2.8.1<br>
<br>
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</blockquote></div>