<div dir="ltr"> <div class="gmail_extra"> <div class="gmail_quote">On Tue, Jul 12, 2016 at 2:36 PM, Chad Versace <<a href="mailto:chad.versace@intel.com" target="_blank">chad.versace@intel.com</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">On Sat 09 Jul 2016, Jason Ekstrand wrote: > --- >Â src/intel/isl/isl.cÂ Â Â Â Â Â Â Â Â | 11 +++++++++++ >Â src/intel/isl/isl.hÂ Â Â Â Â Â Â Â Â | 17 +++++++++++++++++ >Â src/intel/isl/isl_format_layout.csv |Â 1 + >Â src/intel/isl/isl_gen6.cÂ Â Â Â Â Â |Â 8 ++++++++ >Â src/intel/isl/isl_gen7.cÂ Â Â Â Â Â | 10 +++++++++- >Â src/intel/isl/isl_gen8.cÂ Â Â Â Â Â |Â 3 ++- >Â 6 files changed, 48 insertions(+), 2 deletions(-) > > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c > index 8c114a2..9ccdea2 100644 > --- a/src/intel/isl/isl.c > +++ b/src/intel/isl/isl.c > @@ -167,6 +167,16 @@ isl_tiling_get_info(const struct isl_device *dev, >Â Â Â Â break; >Â Â Â } > > +Â Â case ISL_TILING_HIZ: > +Â Â Â /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4 > +Â Â Â Â * 128bpb format.Â The tiling has the same physical dimensions as > +Â Â Â Â * Y-tiling but actually has two HiZ columns per Y-tiled column. > +Â Â Â Â */ > +Â Â Â assert(bs == 16); > +Â Â Â logical_el = isl_extent2d(16, 16); > +Â Â Â phys_B = isl_extent2d(128, 32); > +Â Â Â break; > + >Â Â Â default: >Â Â Â Â unreachable("not reached"); >Â Â Â } /* end switch */ > @@ -221,6 +231,7 @@ isl_surf_choose_tiling(const struct isl_device *dev, >Â Â Â Â CHOOSE(ISL_TILING_LINEAR); >Â Â Â } > > +Â Â CHOOSE(ISL_TILING_HIZ); >Â Â Â CHOOSE(ISL_TILING_Ys); >Â Â Â CHOOSE(ISL_TILING_Yf); >Â Â Â CHOOSE(ISL_TILING_Y0); > diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h > index 85af2d1..9a60bbd 100644 > --- a/src/intel/isl/isl.h > +++ b/src/intel/isl/isl.h > @@ -345,6 +345,14 @@ enum isl_format { >Â Â Â ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 =Â Â Â Â Â Â Â Â Â Â Â Â 638, >Â Â Â ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 =Â Â Â Â Â Â Â Â Â Â Â Â 639, > > +Â Â /* The formats that follow are internal to ISL and as such don't have an > +Â Â * explicit number.Â We'll just let the C compiler assign it for us.Â Any > +Â Â * actual hardware formats *must* come before these in the list. > +Â Â */ > + > +Â Â /* Formats for color compression surfaces */ > +Â Â ISL_FORMAT_HIZ, > + >Â Â Â /* Hardware doesn't understand this out-of-band value */ >Â Â Â ISL_FORMAT_UNSUPPORTED =Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â UINT16_MAX, >Â }; > @@ -392,6 +400,9 @@ enum isl_txc { >Â Â Â ISL_TXC_ETC1, >Â Â Â ISL_TXC_ETC2, >Â Â Â ISL_TXC_ASTC, > + > +Â Â /* Used for auxiliary surface formats */ > +Â Â ISL_TXC_HIZ, </div></div>Yes yes yes! It really is a compressed texture format! <div><div class="h5"> >Â }; > >Â /** > @@ -410,6 +421,7 @@ enum isl_tiling { >Â Â Â ISL_TILING_Y0, /**< Legacy Y tiling */ >Â Â Â ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */ >Â Â Â ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */ > +Â Â ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */ >Â }; > >Â /** > @@ -423,6 +435,7 @@ typedef uint32_t isl_tiling_flags_t; >Â #define ISL_TILING_Y0_BITÂ Â Â Â Â Â Â Â Â (1u << ISL_TILING_Y0) >Â #define ISL_TILING_Yf_BITÂ Â Â Â Â Â Â Â Â (1u << ISL_TILING_Yf) >Â #define ISL_TILING_Ys_BITÂ Â Â Â Â Â Â Â Â (1u << ISL_TILING_Ys) > +#define ISL_TILING_HIZ_BITÂ Â Â Â Â Â Â Â (1u << ISL_TILING_HIZ) >Â #define ISL_TILING_ANY_MASKÂ Â Â Â Â Â Â Â (~0u) >Â #define ISL_TILING_NON_LINEAR_MASKÂ Â Â Â (~ISL_TILING_LINEAR_BIT) > > @@ -505,6 +518,7 @@ typedef uint64_t isl_surf_usage_flags_t; >Â #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BITÂ Â Â (1u << 10) >Â #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BITÂ Â Â (1u << 11) >Â #define ISL_SURF_USAGE_STORAGE_BITÂ Â Â Â Â Â Â (1u << 12) > +#define ISL_SURF_USAGE_HIZ_BITÂ Â Â Â Â Â Â Â Â (1u << 13) >Â /** @} */ > >Â /** > @@ -966,6 +980,9 @@ isl_format_has_bc_compression(enum isl_format fmt) >Â Â Â case ISL_TXC_ETC2: >Â Â Â case ISL_TXC_ASTC: >Â Â Â Â return false; > + > +Â Â case ISL_TXC_HIZ: > +Â Â Â unreachable("Should not be called on an aux surface"); >Â Â Â } > >Â Â Â unreachable("bad texture compression mode"); > diff --git a/src/intel/isl/isl_format_layout.csv b/src/intel/isl/isl_format_layout.csv > index f90fbe0..3e681e8 100644 > --- a/src/intel/isl/isl_format_layout.csv > +++ b/src/intel/isl/isl_format_layout.csv > @@ -314,3 +314,4 @@ ASTC_LDR_2D_10X8_FLT16Â Â Â , 128, 10,Â 8,Â 1, sf16, sf16, sf16, sf16,Â Â Â , >Â ASTC_LDR_2D_10X10_FLT16Â Â Â , 128, 10, 10,Â 1, sf16, sf16, sf16, sf16,Â Â Â ,Â Â Â ,Â Â , linear,Â astc >Â ASTC_LDR_2D_12X10_FLT16Â Â Â , 128, 12, 10,Â 1, sf16, sf16, sf16, sf16,Â Â Â ,Â Â Â ,Â Â , linear,Â astc >Â ASTC_LDR_2D_12X12_FLT16Â Â Â , 128, 12, 12,Â 1, sf16, sf16, sf16, sf16,Â Â Â ,Â Â Â ,Â Â , linear,Â astc > +HIZÂ Â Â Â Â Â Â Â Â Â Â Â Â , 128,Â 8,Â 4,Â 1,Â Â Â ,Â Â Â ,Â Â Â ,Â Â Â ,Â Â Â ,Â Â Â ,Â Â ,Â Â Â Â ,Â Â hiz </div></div>TODO: hiz in script </blockquote><div> </div><div>Thanks to the script being rewritten in a *sane* programming language, there's nothing to change. </div><div>Â </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> <div><div class="h5"> > diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c > index 699aa41..b5050ed 100644 > --- a/src/intel/isl/isl_gen6.c > +++ b/src/intel/isl/isl_gen6.c > @@ -89,6 +89,14 @@ gen6_choose_image_alignment_el(const struct isl_device *dev, >Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â enum isl_msaa_layout msaa_layout, >Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct isl_extent3d *image_align_el) >Â { > +Â Â if (info->format == ISL_FORMAT_HIZ) { > +Â Â Â /* HiZ surfaces are always aligned to 8x16 pixels in the primary surface > +Â Â Â Â * which works out to 2x2 HiZ elments. > +Â Â Â Â */ > +Â Â Â *image_align_el = isl_extent3d(2, 2, 1); > +Â Â Â return; > +Â Â } > + >Â Â Â /* Note that the surface's horizontal image alignment is not programmable >Â Â Â * on Sandybridge. >Â Â Â * > diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c > index d9b0c08..349875f 100644 > --- a/src/intel/isl/isl_gen7.c > +++ b/src/intel/isl/isl_gen7.c > @@ -111,7 +111,8 @@ gen7_choose_msaa_layout(const struct isl_device *dev, >Â Â Â * In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and >Â Â Â * MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED. >Â Â Â */ > -Â Â if (isl_surf_usage_is_depth_or_stencil(info->usage)) > +Â Â if (isl_surf_usage_is_depth_or_stencil(info->usage) || > +Â Â Â Â (info->usage & ISL_SURF_USAGE_HIZ_BIT)) >Â Â Â Â require_interleaved = true; > >Â Â Â /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled > @@ -230,6 +231,13 @@ gen7_filter_tiling(const struct isl_device *dev, >Â Â Â Â *flags &= ~ISL_TILING_W_BIT; >Â Â Â } > > +Â Â /* The HiZ format and tiling always go together */ > +Â Â if (info->format == ISL_FORMAT_HIZ) { > +Â Â Â *flags &= ISL_TILING_HIZ_BIT; > +Â Â } else { > +Â Â Â *flags &= ~ISL_TILING_HIZ_BIT; > +Â Â } > + >Â Â Â if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT | >Â Â Â Â Â Â Â Â Â Â Â Â ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT | >Â Â Â Â Â Â Â Â Â Â Â Â ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) { </div></div>I believe isl_gen7.c needs more updates: Â Â static uint32_t Â Â gen7_choose_halign_el(const struct isl_device *dev, Â Â Â Â Â Â Â Â Â Â Â Â Â const struct isl_surf_init_info *restrict info) Â Â { Â Â +Â Â if (info->format == ISL_FORMAT_HIZ) Â Â +Â Â Â return 2; Â Â + Â Â Â Â if (isl_format_is_compressed(info->format)) Â Â Â Â Â return 1; Â Â ... Â Â static uint32_t Â Â gen7_choose_valign_el(const struct isl_device *dev, Â Â Â Â Â Â Â Â Â Â Â Â Â const struct isl_surf_init_info *restrict info, Â Â Â Â Â Â Â Â Â Â Â Â Â enum isl_tiling tiling) Â Â { Â Â Â Â MAYBE_UNUSED bool require_valign2 = false; Â Â Â Â bool require_valign4 = false; Â Â +Â Â if (info->format == ISL_FORMAT_HIZ) Â Â +Â Â Â return 2; Â Â + Â Â Â Â if (isl_format_is_compressed(info->format)) Â Â Â Â Â return 1; > diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c > index a46427a..62c331c 100644 > --- a/src/intel/isl/isl_gen8.c > +++ b/src/intel/isl/isl_gen8.c > @@ -84,7 +84,8 @@ gen8_choose_msaa_layout(const struct isl_device *dev, >Â Â Â if (isl_format_is_yuv(info->format)) >Â Â Â Â return false; > > -Â Â if (isl_surf_usage_is_depth_or_stencil(info->usage)) > +Â Â if (isl_surf_usage_is_depth_or_stencil(info->usage) || > +Â Â Â Â (info->usage & ISL_SURF_USAGE_HIZ_BIT)) >Â Â Â Â require_interleaved = true; > >Â Â Â if (require_array && require_interleaved) And isl_gen8.c needs the same updates I posted for isl_gen7.c Also, isl.c needs an update in this hunk: Â Â # isl.c Â Â if (isl_surf_usage_is_depth_or_stencil(info->usage)) { Â Â Â /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >> Â Â Â Â * Section <a href="http://6.18.4.7" rel="noreferrer" target="_blank">6.18.4.7</a>: Surface Arrays (p112): Â Â Â Â * Â Â Â Â *Â Â If Surface Array Spacing is set to ARYSPC_FULL (note that Â Â Â Â *Â Â the depth buffer and stencil buffer have an implied value Â Â Â Â *Â Â ARYSPC_FULL): Â Â Â Â */ Â Â Â return ISL_ARRAY_PITCH_SPAN_COMPACT; Â Â } </blockquote></div> </div></div>