<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Aug 11, 2016 at 10:47 AM, Anuj Phogat <span dir="ltr"><<a href="mailto:anuj.phogat@gmail.com" target="_blank">anuj.phogat@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">On Fri, Jul 29, 2016 at 2:30 PM, Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>> wrote:<br>
><br>
><br>
> On Fri, Jul 29, 2016 at 12:32 PM, Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>> wrote:<br>
>><br>
>><br>
>><br>
>> On Thu, Jul 28, 2016 at 6:31 PM, Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br>
>> wrote:<br>
>>><br>
>>> On Jul 28, 2016 7:37 PM, "Anuj Phogat" <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>> wrote:<br>
>>> ><br>
>>> > Fixes the vulkan cts regression in test<br>
>>> > dEQP-VK.api.info.device.<wbr>properties<br>
>>> ><br>
>>> > Cc: Mark Janes <<a href="mailto:mark.a.janes@intel.com">mark.a.janes@intel.com</a>><br>
>>> > Cc: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br>
>>> > Signed-off-by: Anuj Phogat <<a href="mailto:anuj.phogat@gmail.com">anuj.phogat@gmail.com</a>><br>
>>> > ---<br>
>>> > src/intel/vulkan/anv_device.c | 6 +++---<br>
>>> > 1 file changed, 3 insertions(+), 3 deletions(-)<br>
>>> ><br>
>>> > diff --git a/src/intel/vulkan/anv_device.<wbr>c<br>
>>> > b/src/intel/vulkan/anv_device.<wbr>c<br>
>>> > index c2c5153..9fd9683 100644<br>
>>> > --- a/src/intel/vulkan/anv_device.<wbr>c<br>
>>> > +++ b/src/intel/vulkan/anv_device.<wbr>c<br>
>>> > @@ -524,9 +524,9 @@ void anv_<wbr>GetPhysicalDeviceProperties(<br>
>>> > .maxTexelOffset = 7,<br>
>>> > .minTexelGatherOffset = -8,<br>
>>> > .maxTexelGatherOffset = 7,<br>
>>> > - .minInterpolationOffset = 0, /* FIXME */<br>
>>> > - .maxInterpolationOffset = 0, /* FIXME */<br>
>>> > - .<wbr>subPixelInterpolationOffsetBit<wbr>s = 0, /* FIXME */<br>
>>> > + .minInterpolationOffset = -0.5,<br>
>>> > + .maxInterpolationOffset = 0.5,<br>
><br>
> Correction: maxInterpolationOffset = 0.4375<br>
> From Vulkan 1.0 spec:<br>
> "<br>
> If subPixelInterpolationOffsetBit<wbr>s is 4, this provides increments of (1/24)<br>
> = 0.0625, and thus the range of supported interpolation offsets would be<br>
> [-0.5, 0.4375].<br>
> "<br>
</div></div>Jason, other than above correction, is there anything else you want me<br>
to address in V2 of this patch ?<br></blockquote><div><br></div><div>No, I think what you have is fine. Assuming that's the only change, v2 will be<br><br></div><div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">
>>><br>
>>> > + .<wbr>subPixelInterpolationOffsetBit<wbr>s = 4,<br>
>>><br>
>>> I looked and neither gen7_pipeline.c nor gen8_pipeline.c set the subpixel<br>
>>> precision so we get a default of enum value 0 which is 8 bits. We should<br>
>>> probably be explicitly setting it to something. I think 4 is probably fine<br>
>>> but we should be seeing it.<br>
>><br>
>> I think you're talking about "Vertex Sub Pixel Precision Select" in<br>
>> 3DSTATE_SF. Yes, we are setting a default value of zero which is 8 bits in<br>
>> both OpenGL and Vulkan. This meets the minimum requirement of 4 bits for<br>
>> GL_SUBPIXEL_BITS. Yes, it'll be nicer to make it more obvious what we are<br>
>> setting here.<br>
>><br>
>> The value we are defining in this patch is subPixelInterpolationOffsetBit<wbr>s<br>
>> (GL_FRAGMENT_INTERPOLATION_<wbr>OFFSET_BITS in OpenGL). I found no option of<br>
>> setting it on Intel Hardware. I just replicated what we do in i965 and made<br>
>> the CTS test happy again.<br>
>><br>
>> Looks unrelated but there is this another thing 'viewportSubPixelBits'<br>
>> which is initialized to 13 in Vulkan but 0 (required min. value) in i965.<br>
>> Again found no option of setting on Intel hardware.So, a similar case to<br>
>> subPixelInterpolationOffsetBit<wbr>s.<br>
>>><br>
>>> As a side note, I think we could probably combine 3DSTATE_SF and<br>
>>> 3DSTATE_RASTER setup between gen7 and gen8 (and move it to<br>
>>> genX_pipeline_until.h). We'd probably have to do some #define trick like we<br>
>>> did for 3DSTATE_SBE and 3DSTATE_SBE_SWIZ because the two packets are<br>
>>> combined on gen7 and split on gen8.<br>
>><br>
>> I'll look in to it.<br>
>><br>
>>><br>
>>> > .maxFramebufferWidth = (1 << 14),<br>
>>> > .maxFramebufferHeight = (1 << 14),<br>
>>> > .maxFramebufferLayers = (1 << 10),<br>
>>> > --<br>
>>> > 2.5.5<br>
>>> ><br>
>><br>
>><br>
><br>
</div></div></blockquote></div><br></div></div>