<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Aug 17, 2016 at 12:17 AM, Pohjolainen, Topi <span dir="ltr"><<a href="mailto:topi.pohjolainen@intel.com" target="_blank">topi.pohjolainen@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On Tue, Jul 26, 2016 at 03:11:10PM -0700, Jason Ekstrand wrote:<br>
> The previous HiZ support was bogus because all of get_aux_isl_surf looked<br>
> at mt->mcs_mt directly.  For HiZ buffers, you need to look at either<br>
> mt->hiz_buf or mt->hiz_buf->mt.<br>
<br>
</span>Makes a lot more sense:<br>
<br>
Reviewed-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
<br>
I wonder how it worked before, did the mcs and hiz just happen to match<br>
well enough...<br></blockquote><div><br></div><div>We never used an isl_surf for hiz<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div><div class="h5"><br>
> ---<br>
>  src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c | 41 ++++++++++++++++++---------<br>
>  1 file changed, 28 insertions(+), 13 deletions(-)<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
> index f762106..40a561f 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c<br>
> @@ -3189,17 +3189,32 @@ intel_miptree_get_aux_isl_<wbr>surf(struct brw_context *brw,<br>
>                                 struct isl_surf *surf,<br>
>                                 enum isl_aux_usage *usage)<br>
>  {<br>
> -   /* Figure out the layout */<br>
> -   if (_mesa_get_format_base_format(<wbr>mt->format) == GL_DEPTH_COMPONENT) {<br>
> +   uint32_t aux_pitch, aux_qpitch;<br>
> +   if (mt->mcs_mt) {<br>
> +      aux_pitch = mt->mcs_mt->pitch;<br>
> +      aux_qpitch = mt->mcs_mt->qpitch;<br>
> +<br>
> +      if (mt->num_samples > 1) {<br>
> +         assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);<br>
> +         *usage = ISL_AUX_USAGE_MCS;<br>
> +      } else if (intel_miptree_is_lossless_<wbr>compressed(brw, mt)) {<br>
> +         assert(brw->gen >= 9);<br>
> +         *usage = ISL_AUX_USAGE_CCS_E;<br>
> +      } else if (mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS) {<br>
> +         *usage = ISL_AUX_USAGE_CCS_D;<br>
> +      } else {<br>
> +         unreachable("Invalid MCS miptree");<br>
> +      }<br>
> +   } else if (mt->hiz_buf) {<br>
> +      if (mt->hiz_buf->mt) {<br>
> +         aux_pitch = mt->hiz_buf->mt->pitch;<br>
> +         aux_qpitch = mt->hiz_buf->mt->qpitch;<br>
> +      } else {<br>
> +         aux_pitch = mt->hiz_buf->pitch;<br>
> +         aux_qpitch = mt->hiz_buf->qpitch;<br>
> +      }<br>
> +<br>
>        *usage = ISL_AUX_USAGE_HIZ;<br>
> -   } else if (mt->num_samples > 1) {<br>
> -      assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);<br>
> -      *usage = ISL_AUX_USAGE_MCS;<br>
> -   } else if (intel_miptree_is_lossless_<wbr>compressed(brw, mt)) {<br>
> -      assert(brw->gen >= 9);<br>
> -      *usage = ISL_AUX_USAGE_CCS_E;<br>
> -   } else if (mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS) {<br>
> -      *usage = ISL_AUX_USAGE_CCS_D;<br>
>     } else {<br>
>        *usage = ISL_AUX_USAGE_NONE;<br>
>        return;<br>
> @@ -3211,7 +3226,7 @@ intel_miptree_get_aux_isl_<wbr>surf(struct brw_context *brw,<br>
>     /* Figure out the format and tiling of the auxiliary surface */<br>
>     switch (*usage) {<br>
>     case ISL_AUX_USAGE_NONE:<br>
> -      unreachable("Invalid MCS miptree");<br>
> +      unreachable("Invalid auxiliary usage");<br>
><br>
>     case ISL_AUX_USAGE_HIZ:<br>
>        isl_surf_get_hiz_surf(&brw-><wbr>isl_dev, surf, surf);<br>
> @@ -3250,7 +3265,7 @@ intel_miptree_get_aux_isl_<wbr>surf(struct brw_context *brw,<br>
>     }<br>
><br>
>     /* We want the pitch of the actual aux buffer. */<br>
> -   surf->row_pitch = mt->mcs_mt->pitch;<br>
> +   surf->row_pitch = aux_pitch;<br>
><br>
>     /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows<br>
>      * is in elements.  This doesn't match intel_mipmap_tree::qpitch which is<br>
> @@ -3258,7 +3273,7 @@ intel_miptree_get_aux_isl_<wbr>surf(struct brw_context *brw,<br>
>      * compression block height.<br>
>      */<br>
>     surf->array_pitch_el_rows =<br>
> -      mt->mcs_mt->qpitch / isl_format_get_layout(surf-><wbr>format)->bh;<br>
> +      aux_qpitch / isl_format_get_layout(surf-><wbr>format)->bh;<br>
>  }<br>
><br>
>  union isl_color_value<br>
> --<br>
> 2.5.0.400.gff86faf<br>
><br>
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</blockquote></div><br></div></div>