<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Wed, Aug 31, 2016 at 8:17 AM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@intel.com" target="_blank">topi.pohjolainen@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Once mcs buffer gets allocated without delay for lossless<br>
compression (same as we do for msaa), one gets regression in:<br>
<br>
GL45-CTS.texture_barrier_ARB.<wbr>same-texel-rw<br>
<br>
Setting the auxiliary surface for both sampling engine and data<br>
port seems to fix this. I haven't found any hardware documentation<br>
backing this though.<br>
<br>
Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
 src/mesa/drivers/dri/i965/brw_<wbr>wm_surface_state.c | 46 ++++++++++++++++++++++--<br>
 1 file changed, 43 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
index bfd973b..5cd27ef 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
@@ -72,6 +72,48 @@ static const struct surface_state_info surface_state_infos[] = {<br>
    [9] = {16, 64, 8,  10, SKL_MOCS_WB,  SKL_MOCS_PTE},<br>
 };<br>
<br>
+static bool<br>
+brw_needs_aux_surface(const struct brw_context *brw,<br>
+                      const struct intel_mipmap_tree *mt,<br>
+                      const struct isl_view *view)<br>
+{<br>
+   if (!mt->mcs_mt)<br>
+      return false;<br>
+<br>
+   if (view->usage & ISL_SURF_USAGE_RENDER_TARGET_<wbr>BIT)<br>
+      return true;<br>
+<br>
+   const bool is_lossless_compressed =<br>
+      intel_miptree_is_lossless_<wbr>compressed(brw, mt);<br>
+   const bool view_format_lossless_<wbr>compressed =<br>
+       isl_format_supports_lossless_<wbr>compression(brw->intelScreen-><wbr>devinfo,<br>
+                                                view->format);<br>
+<br>
+   /* If the underlying surface is compressed but it is sampled using a<br>
+    * format that the sampling engine doesn't support as compressed, there<br>
+    * is no alternative but to treat the surface as non-compressed.<br>
+    */<br></blockquote><div><br></div><div>Does this even work?  I mean, can you render to a texture with one format and texture from it with another and still use color compression?<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+   if (is_lossless_compressed && !view_format_lossless_<wbr>compressed) {<br></blockquote><div><br></div><div>This is more of a change in behavior than the commit message says.  We should probably make the commit message a bit better.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+      /* Logic elsewhere needs to take care to resolve the color buffer prior<br>
+       * to sampling it as non-compressed.<br>
+       */<br>
+      assert(mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_<wbr>RESOLVED);<br>
+      return false;<br>
+   }<br>
+<br>
+   /* In practise it looks that setting the same lossless compressed surface<br>
+    * to be sampled without auxiliary surface and to be written with auxiliary<br>
+    * surface confuses the hardware.<br>
+    * Currently there is no direct way of knowing if render pass will use the<br>
+    * sane surface as render target and therefore simply use the auxiliary<br>
+    * surface unconditionally here.<br>
+    */<br>
+   if (is_lossless_compressed)<br>
+      return true;<br></blockquote><div><br></div><div>This makes a lot of sense.  If we're sampling from and rendering to the same surface, we'd better have the compression buffer for both.  That said, if we ever bind a compressed buffer as a render target with a texture-viewed version as a source (as per above), we're going to have a problem...<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
+   return mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_<wbr>RESOLVED;<br>
+}<br>
+<br>
 static void<br>
 brw_emit_surface_state(struct brw_context *brw,<br>
                        struct intel_mipmap_tree *mt,<br>
@@ -135,9 +177,7 @@ brw_emit_surface_state(struct brw_context *brw,<br>
    struct isl_surf *aux_surf = NULL, aux_surf_s;<br>
    uint64_t aux_offset = 0;<br>
    enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;<br>
-   if (mt->mcs_mt &&<br>
-       ((view.usage & ISL_SURF_USAGE_RENDER_TARGET_<wbr>BIT) ||<br>
-        mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_<wbr>RESOLVED)) {<br>
+   if (brw_needs_aux_surface(brw, mt, &view)) {<br>
       intel_miptree_get_aux_isl_<wbr>surf(brw, mt, &aux_surf_s, &aux_usage);<br>
       aux_surf = &aux_surf_s;<br>
       assert(mt->mcs_mt->offset == 0);<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.5.5<br>
<br>
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