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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [SNB, BXT] up to 40% perf drop from "loader/dri3: Overhaul dri3_update_num_back" commit"
href="https://bugs.freedesktop.org/show_bug.cgi?id=97549">97549</a>
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<th>Summary</th>
<td>[SNB, BXT] up to 40% perf drop from "loader/dri3: Overhaul dri3_update_num_back" commit
</td>
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<th>Product</th>
<td>Mesa
</td>
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<th>Version</th>
<td>git
</td>
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<th>Hardware</th>
<td>x86-64 (AMD64)
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>normal
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<th>Priority</th>
<td>high
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<th>Component</th>
<td>Other
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<th>Assignee</th>
<td>mesa-dev@lists.freedesktop.org
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<th>Reporter</th>
<td>eero.t.tamminen@intel.com
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<th>QA Contact</th>
<td>mesa-dev@lists.freedesktop.org
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<th>CC</th>
<td>michel@daenzer.net
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<pre>Following commit regresses performance hugely with DRI3 in synthetic benchmarks
both on Sandybridge and Broxton.
commit 1e3218bc5ba2b739261f0c0bacf4eb662d377236
Author: Michel Dänzer <<a href="mailto:michel.daenzer@amd.com">michel.daenzer@amd.com</a>>
AuthorDate: Wed Aug 17 17:02:04 2016 +0900
Commit: Michel Dänzer <<a href="mailto:michel@daenzer.net">michel@daenzer.net</a>>
CommitDate: Thu Aug 25 17:40:24 2016 +0900
loader/dri3: Overhaul dri3_update_num_back
Always use 3 buffers when flipping. With only 2 buffers, we have to wait
for a flip to complete (which takes non-0 time even with asynchronous
flips) before we can start working on the next frame. We were previously
only using 2 buffers for flipping if the X server supports asynchronous
flips, even when we're not using asynchronous flips. This could result
in bad performance (the referenced bug report is an extreme case, where
the inter-frame stalls were preventing the GPU from reaching its maximum
clocks).
I couldn't measure any performance boost using 4 buffers with flipping.
Performance actually seemed to go down slightly, but that might have
been just noise.
Without flipping, a single back buffer is enough for swap interval 0,
but we need to use 2 back buffers when the swap interval is non-0,
otherwise we have to wait for the swap interval to pass before we can
start working on the next frame. This condition was previously reversed.
Cc: "12.0 11.2" <<a href="mailto:mesa-stable@lists.freedesktop.org">mesa-stable@lists.freedesktop.org</a>>
Bugzilla: <a class="bz_bug_link
bz_status_NEW "
title="NEW - [bisected] R9 290 low performance in Linux 4.7"
href="show_bug.cgi?id=97260">https://bugs.freedesktop.org/show_bug.cgi?id=97260</a>
Reviewed-by: Frank Binns <<a href="mailto:frank.binns@imgtec.com">frank.binns@imgtec.com</a>>
Reviewed-by: Eric Anholt <<a href="mailto:eric@anholt.net">eric@anholt.net</a>>
Reverting the batch restores earlier performance (bisect done on Broxton,
revert tested on Sandybridge, so same commit is problem for both).
Impact is larger for tests with higher FPS, and naturally affects only onscreen
versions of the tests. Both fullscreen and windowed+composited tests were
affected.
On Sandybridge impact is up to 35% (SynMark Batch tests), 25% in GpuTest
Triangle test, and less in other tests.
On Broxton the drop affects more tests (due to better GPU, heavier tests have
higher FPS), even few tests that are normally fully ALU bound:
* SynMark v6: up to 40% (Batch tests)
* GfxBench v4: 35% ALU, 25% Driver, 10% Tess tests
* Lightsmark 2008: 20%
* GpuTest 0.7: 15% Triangle, Julia32 & Plot3D tests
* GLB 2.7: 10% Egypt
The change doesn't seem to affect HSW, BDW nor SKL. I don't know why.
Issue doesn't seem to be related to FPS (occasionally) being limited to some
multiple of 60 FPS like in the earlier DRI3 perf bug. My assumption is that
the buffering change indirectly affects some memory setting, but I don't know
what, as SNB & BXT different in that respect:
* SNB has LLC, but BXT doesn't
* AFAIK Intel DDX supports SNA for SNB, but not yet for BXT</pre>
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