<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Tue, Sep 6, 2016 at 8:16 AM, Pohjolainen, Topi <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On Tue, Sep 06, 2016 at 07:54:16AM -0700, Jason Ekstrand wrote:<br>
> On Tue, Sep 6, 2016 at 12:28 AM, Topi Pohjolainen<br>
</span>> <[1]<a href="mailto:topi.pohjolainen@gmail.com">topi.pohjolainen@gmail.com</a><wbr>> wrote:<br>
><br>
> Signed-off-by: Topi Pohjolainen <[2]<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a><wbr>><br>
<div><div class="h5">> ---<br>
> src/mesa/drivers/dri/i965/brw_<wbr>context.c | 16<br>
> ++++++++++++++++<br>
> src/mesa/drivers/dri/i965/brw_<wbr>context.h | 10 ++++++++++<br>
> src/mesa/drivers/dri/i965/brw_<wbr>wm_surface_state.c | 12 ++++++++++--<br>
> 3 files changed, 36 insertions(+), 2 deletions(-)<br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_context.c<br>
> b/src/mesa/drivers/dri/i965/<wbr>brw_context.c<br>
> index b880b4f..c5c6fdd 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>brw_context.c<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>brw_context.c<br>
> @@ -197,6 +197,22 @@ intel_texture_view_requires_<wbr>resolve(struct<br>
> brw_context *brw,<br>
> _mesa_get_format_name(intel_<wbr>tex->_Format),<br>
> _mesa_get_format_name(intel_<wbr>tex->mt->format));<br>
> + const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;<br>
> + for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {<br>
> + const struct intel_renderbuffer *irb =<br>
> + intel_renderbuffer(fb->_<wbr>ColorDrawBuffers[i]);<br>
> +<br>
> + /* In case the same surface is also used for rendering one<br>
> needs to<br>
> + * disable the compression.<br>
> + */<br>
> + brw->draw_aux_buffer_disabled[<wbr>i] = intel_tex->mt->bo ==<br>
> irb->mt->bo;<br>
<br>
</div></div>This loop goes thru all render surfaces and explicitly sets the flag. In<br>
other words all flags are reset before uploading state - no need for<br>
separate memset.<br></blockquote><div><br></div><div>Ugh... then it is busted if you have multiple render targets *or* multiple textures where the one being rendered to isn't the last one. Only the render buffer for the last bound texture will get the buffer_aux_buffer_disabled[] bit set. We really need a reset and set-of-disable-needed model.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div class="h5">
> +<br>
> + if (brw->draw_aux_buffer_<wbr>disabled[i]) {<br>
> + perf_debug("Sampling renderbuffer with non-compressible<br>
> format - "<br>
> + "turning off compression");<br>
> + }<br>
> + }<br>
> +<br>
> return true;<br>
> }<br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
> b/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
> index 12ac8af..074d554 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
> @@ -1333,6 +1333,16 @@ struct brw_context<br>
> struct brw_fast_clear_state *fast_clear_state;<br>
> + /* Array of flags telling if auxiliary buffer is disabled for<br>
> corresponding<br>
> + * renderbuffer. If draw_aux_buffer_disabled[i] is set then use<br>
> of<br>
> + * auxiliary buffer for gl_framebuffer::_<wbr>ColorDrawBuffers[i] is<br>
> + * disabled.<br>
> + * This is needed in case the same underlying buffer is also<br>
> configured<br>
> + * to be sampled but with a format that the sampling engine<br>
> can't treat<br>
> + * compressed or fast cleared.<br>
> + */<br>
> + bool draw_aux_buffer_disabled[MAX_<wbr>DRAW_BUFFERS];<br>
><br>
> I like the way you handled this. It's nice and clean. However, I<br>
> don't see where you memset draw_aux_buffer_disabled to 0 to reset it.<br>
> Did that just go missing?<br>
><br>
> +<br>
> __DRIcontext *driContext;<br>
> struct intel_screen *intelScreen;<br>
> };<br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
> b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
> index 073919e..af102a9 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
> @@ -56,6 +56,7 @@<br>
> enum {<br>
> INTEL_RENDERBUFFER_LAYERED = 1 << 0,<br>
> + INTEL_RENDERBUFFER_AUX_<wbr>DISABLED = 1 << 1,<br>
> };<br>
> struct surface_state_info {<br>
> @@ -194,6 +195,10 @@ brw_update_renderbuffer_<wbr>surface(struct<br>
> brw_context *brw,<br>
> struct intel_renderbuffer *irb = intel_renderbuffer(rb);<br>
> struct intel_mipmap_tree *mt = irb->mt;<br>
> + if (brw->gen < 9) {<br>
> + assert(!(flags & INTEL_RENDERBUFFER_AUX_<wbr>DISABLED));<br>
> + }<br>
> +<br>
> assert(brw_render_target_<wbr>supported(brw, rb));<br>
> intel_miptree_used_for_<wbr>rendering(mt);<br>
> @@ -885,6 +890,7 @@ gen4_update_renderbuffer_<wbr>surface(struct<br>
> brw_context *brw,<br>
> /* BRW_NEW_FS_PROG_DATA */<br>
> assert(!(flags & INTEL_RENDERBUFFER_LAYERED));<br>
> + assert(!(flags & INTEL_RENDERBUFFER_AUX_<wbr>DISABLED));<br>
> if (rb->TexImage && !brw->has_surface_tile_offset) {<br>
> intel_renderbuffer_get_tile_<wbr>offsets(irb, &tile_x, &tile_y);<br>
> @@ -987,8 +993,10 @@ brw_update_renderbuffer_<wbr>surfaces(struct<br>
> brw_context *brw,<br>
> if (fb->_NumColorDrawBuffers >= 1) {<br>
> for (i = 0; i < fb->_NumColorDrawBuffers; i++) {<br>
> const uint32_t surf_index = render_target_start + i;<br>
> - const int flags =<br>
> - _mesa_geometric_layers(fb) > 0 ?<br>
> INTEL_RENDERBUFFER_LAYERED : 0;<br>
> + const int flags = (_mesa_geometric_layers(fb) > 0 ?<br>
> + INTEL_RENDERBUFFER_LAYERED : 0) |<br>
> + (brw->draw_aux_buffer_<wbr>disabled[i] ?<br>
> + INTEL_RENDERBUFFER_AUX_<wbr>DISABLED : 0);<br>
> if (intel_renderbuffer(fb->_<wbr>ColorDrawBuffers[i])) {<br>
> surf_offset[surf_index] =<br>
> --<br>
> 2.5.5<br>
> ______________________________<wbr>_________________<br>
> mesa-dev mailing list<br>
</div></div>> [3]<a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.<wbr>org</a><br>
> [4]<a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.<wbr>org/mailman/listinfo/mesa-dev</a><br>
><br>
> References<br>
><br>
> 1. mailto:<a href="mailto:topi.pohjolainen@gmail.com">topi.pohjolainen@gmail.<wbr>com</a><br>
> 2. mailto:<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.<wbr>com</a><br>
> 3. mailto:<a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.<wbr>freedesktop.org</a><br>
> 4. <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/<wbr>mailman/listinfo/mesa-dev</a><br>
</blockquote></div><br></div></div>