<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Tue, Sep 6, 2016 at 12:28 AM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
src/mesa/drivers/dri/i965/brw_<wbr>context.c | 16 ++++++++++++++++<br>
src/mesa/drivers/dri/i965/brw_<wbr>context.h | 10 ++++++++++<br>
src/mesa/drivers/dri/i965/brw_<wbr>wm_surface_state.c | 12 ++++++++++--<br>
3 files changed, 36 insertions(+), 2 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_context.c b/src/mesa/drivers/dri/i965/<wbr>brw_context.c<br>
index b880b4f..c5c6fdd 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_context.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_context.c<br>
@@ -197,6 +197,22 @@ intel_texture_view_requires_<wbr>resolve(struct brw_context *brw,<br>
_mesa_get_format_name(intel_<wbr>tex->_Format),<br>
_mesa_get_format_name(intel_<wbr>tex->mt->format));<br>
<br>
+ const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;<br>
+ for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {<br>
+ const struct intel_renderbuffer *irb =<br>
+ intel_renderbuffer(fb->_<wbr>ColorDrawBuffers[i]);<br>
+<br>
+ /* In case the same surface is also used for rendering one needs to<br>
+ * disable the compression.<br>
+ */<br>
+ brw->draw_aux_buffer_disabled[<wbr>i] = intel_tex->mt->bo == irb->mt->bo;<br>
+<br>
+ if (brw->draw_aux_buffer_<wbr>disabled[i]) {<br>
+ perf_debug("Sampling renderbuffer with non-compressible format - "<br>
+ "turning off compression");<br>
+ }<br>
+ }<br>
+<br>
return true;<br>
}<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_context.h b/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
index 12ac8af..074d554 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
@@ -1333,6 +1333,16 @@ struct brw_context<br>
<br>
struct brw_fast_clear_state *fast_clear_state;<br>
<br>
+ /* Array of flags telling if auxiliary buffer is disabled for corresponding<br>
+ * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of<br>
+ * auxiliary buffer for gl_framebuffer::_<wbr>ColorDrawBuffers[i] is<br>
+ * disabled.<br>
+ * This is needed in case the same underlying buffer is also configured<br>
+ * to be sampled but with a format that the sampling engine can't treat<br>
+ * compressed or fast cleared.<br>
+ */<br>
+ bool draw_aux_buffer_disabled[MAX_<wbr>DRAW_BUFFERS];<br></blockquote><div><br></div><div>I like the way you handled this. It's nice and clean. However, I don't see where you memset draw_aux_buffer_disabled to 0 to reset it. Did that just go missing?<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
__DRIcontext *driContext;<br>
struct intel_screen *intelScreen;<br>
};<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
index 073919e..af102a9 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
@@ -56,6 +56,7 @@<br>
<br>
enum {<br>
INTEL_RENDERBUFFER_LAYERED = 1 << 0,<br>
+ INTEL_RENDERBUFFER_AUX_<wbr>DISABLED = 1 << 1,<br>
};<br>
<br>
struct surface_state_info {<br>
@@ -194,6 +195,10 @@ brw_update_renderbuffer_<wbr>surface(struct brw_context *brw,<br>
struct intel_renderbuffer *irb = intel_renderbuffer(rb);<br>
struct intel_mipmap_tree *mt = irb->mt;<br>
<br>
+ if (brw->gen < 9) {<br>
+ assert(!(flags & INTEL_RENDERBUFFER_AUX_<wbr>DISABLED));<br>
+ }<br>
+<br>
assert(brw_render_target_<wbr>supported(brw, rb));<br>
intel_miptree_used_for_<wbr>rendering(mt);<br>
<br>
@@ -885,6 +890,7 @@ gen4_update_renderbuffer_<wbr>surface(struct brw_context *brw,<br>
/* BRW_NEW_FS_PROG_DATA */<br>
<br>
assert(!(flags & INTEL_RENDERBUFFER_LAYERED));<br>
+ assert(!(flags & INTEL_RENDERBUFFER_AUX_<wbr>DISABLED));<br>
<br>
if (rb->TexImage && !brw->has_surface_tile_offset) {<br>
intel_renderbuffer_get_tile_<wbr>offsets(irb, &tile_x, &tile_y);<br>
@@ -987,8 +993,10 @@ brw_update_renderbuffer_<wbr>surfaces(struct brw_context *brw,<br>
if (fb->_NumColorDrawBuffers >= 1) {<br>
for (i = 0; i < fb->_NumColorDrawBuffers; i++) {<br>
const uint32_t surf_index = render_target_start + i;<br>
- const int flags =<br>
- _mesa_geometric_layers(fb) > 0 ? INTEL_RENDERBUFFER_LAYERED : 0;<br>
+ const int flags = (_mesa_geometric_layers(fb) > 0 ?<br>
+ INTEL_RENDERBUFFER_LAYERED : 0) |<br>
+ (brw->draw_aux_buffer_<wbr>disabled[i] ?<br>
+ INTEL_RENDERBUFFER_AUX_<wbr>DISABLED : 0);<br>
<br>
if (intel_renderbuffer(fb->_<wbr>ColorDrawBuffers[i])) {<br>
surf_offset[surf_index] =<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.5.5<br>
<br>
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</font></span></blockquote></div><br></div></div>