On Sep 7, 2016 10:24 AM, "Topi Pohjolainen" <<a href="mailto:topi.pohjolainen@gmail.com">topi.pohjolainen@gmail.com</a>> wrote: > > v3: > - Actually set the flags when needed instead of falsely > overwriting them (Jason). > - Use more generic name for flag (dropped RENDERBUFFER) > - Consult also shader images > > Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>> > --- > src/mesa/drivers/dri/i965/brw_context.c | 32 ++++++++++++++++++++++++ > src/mesa/drivers/dri/i965/brw_context.h | 10 ++++++++ > src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++++++-- > 3 files changed, 52 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c > index b880b4f..0379cc0 100644 > --- a/src/mesa/drivers/dri/i965/brw_context.c > +++ b/src/mesa/drivers/dri/i965/brw_context.c > @@ -168,6 +168,24 @@ intel_update_framebuffer(struct gl_context *ctx, > fb->DefaultGeometry.NumSamples); > } > > +static bool > +intel_disable_rb_aux_buffer(struct brw_context *brw, const drm_intel_bo *bo) > +{ > + const struct gl_framebuffer *fb = brw->ctx.DrawBuffer; > + bool found = false; > + > + for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) { > + const struct intel_renderbuffer *irb = > + intel_renderbuffer(fb->_ColorDrawBuffers[i]); > + > + if (irb->mt->bo == bo) { > + found = brw->draw_aux_buffer_disabled[i] = true; Thanks for not breaking. You could, in theory have two different array slices of the same underlying texture bound as different render targets so we can't assume a one-to-one mapping of miptrees to render target indices. Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>> > + } > + } > + > + return found; > +} > + > /* On Gen9 color buffers may be compressed by the hardware (lossless > * compression). There are, however, format restrictions and care needs to be > * taken that the sampler engine is capable for re-interpreting a buffer with > @@ -197,6 +215,10 @@ intel_texture_view_requires_resolve(struct brw_context *brw, > _mesa_get_format_name(intel_tex->_Format), > _mesa_get_format_name(intel_tex->mt->format)); > > + if (intel_disable_rb_aux_buffer(brw, intel_tex->mt->bo)) > + perf_debug("Sampling renderbuffer with non-compressible format - " > + "turning off compression"); > + > return true; > } > > @@ -220,6 +242,9 @@ intel_update_state(struct gl_context * ctx, GLuint new_state) > if (depth_irb) > intel_renderbuffer_resolve_hiz(brw, depth_irb); > > + memset(brw->draw_aux_buffer_disabled, 0, > + sizeof(brw->draw_aux_buffer_disabled)); > + > /* Resolve depth buffer and render cache of each enabled texture. */ > int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit; > for (int i = 0; i <= maxEnabledUnit; i++) { > @@ -262,6 +287,13 @@ intel_update_state(struct gl_context * ctx, GLuint new_state) > * surfaces need to be resolved prior to accessing them. > */ > intel_miptree_resolve_color(brw, tex_obj->mt, 0); > + > + if (brw->gen >= 9 && > + intel_disable_rb_aux_buffer(brw, tex_obj->mt->bo)) { > + perf_debug("Using renderbuffer as shader image - turning " > + "off compression"); > + } > + > brw_render_cache_set_check_flush(brw, tex_obj->mt->bo); > } > } > diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h > index 12ac8af..074d554 100644 > --- a/src/mesa/drivers/dri/i965/brw_context.h > +++ b/src/mesa/drivers/dri/i965/brw_context.h > @@ -1333,6 +1333,16 @@ struct brw_context > > struct brw_fast_clear_state *fast_clear_state; > > + /* Array of flags telling if auxiliary buffer is disabled for corresponding > + * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of > + * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is > + * disabled. > + * This is needed in case the same underlying buffer is also configured > + * to be sampled but with a format that the sampling engine can't treat > + * compressed or fast cleared. > + */ > + bool draw_aux_buffer_disabled[MAX_DRAW_BUFFERS]; > + > __DRIcontext *driContext; > struct intel_screen *intelScreen; > }; > diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > index 073919e..c1273c5 100644 > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > @@ -56,6 +56,7 @@ > > enum { > INTEL_RENDERBUFFER_LAYERED = 1 << 0, > + INTEL_AUX_BUFFER_DISABLED = 1 << 1, > }; > > struct surface_state_info { > @@ -194,6 +195,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw, > struct intel_renderbuffer *irb = intel_renderbuffer(rb); > struct intel_mipmap_tree *mt = irb->mt; > > + if (brw->gen < 9) { > + assert(!(flags & INTEL_AUX_BUFFER_DISABLED)); > + } > + > assert(brw_render_target_supported(brw, rb)); > intel_miptree_used_for_rendering(mt); > > @@ -885,6 +890,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, > /* BRW_NEW_FS_PROG_DATA */ > > assert(!(flags & INTEL_RENDERBUFFER_LAYERED)); > + assert(!(flags & INTEL_AUX_BUFFER_DISABLED)); > > if (rb->TexImage && !brw->has_surface_tile_offset) { > intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y); > @@ -987,8 +993,10 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw, > if (fb->_NumColorDrawBuffers >= 1) { > for (i = 0; i < fb->_NumColorDrawBuffers; i++) { > const uint32_t surf_index = render_target_start + i; > - const int flags = > - _mesa_geometric_layers(fb) > 0 ? INTEL_RENDERBUFFER_LAYERED : 0; > + const int flags = (_mesa_geometric_layers(fb) > 0 ? > + INTEL_RENDERBUFFER_LAYERED : 0) | > + (brw->draw_aux_buffer_disabled[i] ? > + INTEL_AUX_BUFFER_DISABLED : 0); > > if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) { > surf_offset[surf_index] = > -- > 2.5.5 > > _______________________________________________ > mesa-dev mailing list ><a href="mailto:mesa-dev@lists.freedesktop.org"> mesa-dev@lists.freedesktop.org</a> ><a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev"> https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a>