<p dir="ltr"></p>
<p dir="ltr">On Sep 15, 2016 12:05 AM, "Timothy Arceri" <<a href="mailto:timothy.arceri@collabora.com">timothy.arceri@collabora.com</a>> wrote:<br>
><br>
> This moves the nir_lower_indirect_derefs() call into<br>
> brw_preprocess_nir() so thats is called by both OpenGL and Vulkan<br>
> and removes that call to the old GLSL IR pass<br>
> lower_variable_index_to_cond_assign()<br>
><br>
> We want to do this pass in nir to be able to move loop unrolling<br>
> to nir.<br>
><br>
> There is a increase of 1-3 instructions in a small number of shaders,<br>
> and 2 Kerbal Space program shaders that increase by 32 instructions.<br>
><br>
> Shader-db results BDW:<br>
><br>
> total instructions in shared programs: 8705873 -> 8706194 (0.00%)<br>
> instructions in affected programs: 32515 -> 32836 (0.99%)<br>
> helped: 3<br>
> HURT: 79<br>
><br>
> total cycles in shared programs: 74618120 -> 74583476 (-0.05%)<br>
> cycles in affected programs: 528104 -> 493460 (-6.56%)<br>
> helped: 47<br>
> HURT: 37<br>
><br>
> LOST:   2<br>
> GAINED: 0<br>
> ---<br>
>  src/intel/vulkan/anv_pipeline.c        | 10 ----------<br>
>  src/mesa/drivers/dri/i965/brw_link.cpp | 26 ++++++++++++++------------<br>
>  src/mesa/drivers/dri/i965/brw_nir.c    | 12 ++++++++++++<br>
>  3 files changed, 26 insertions(+), 22 deletions(-)<br>
><br>
> diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c<br>
> index f96fe22..f292f0b 100644<br>
> --- a/src/intel/vulkan/anv_pipeline.c<br>
> +++ b/src/intel/vulkan/anv_pipeline.c<br>
> @@ -183,16 +183,6 @@ anv_shader_compile_to_nir(struct anv_device *device,<br>
><br>
>     nir_shader_gather_info(nir, entry_point->impl);<br>
><br>
> -   nir_variable_mode indirect_mask = 0;<br>
> -   if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)<br>
> -      indirect_mask |= nir_var_shader_in;<br>
> -   if (compiler->glsl_compiler_options[stage].EmitNoIndirectOutput)<br>
> -      indirect_mask |= nir_var_shader_out;<br>
> -   if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)<br>
> -      indirect_mask |= nir_var_local;<br>
> -<br>
> -   nir_lower_indirect_derefs(nir, indirect_mask);<br>
> -<br>
>     return nir;<br>
>  }<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp<br>
> index 2b1fa61..41791d4 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_link.cpp<br>
> +++ b/src/mesa/drivers/dri/i965/brw_link.cpp<br>
> @@ -139,18 +139,20 @@ process_glsl_ir(gl_shader_stage stage,<br>
><br>
>     do_copy_propagation(shader->ir);<br>
><br>
> -   bool lowered_variable_indexing =<br>
> -      lower_variable_index_to_cond_assign((gl_shader_stage)stage,<br>
> -                                          shader->ir,<br>
> -                                          options->EmitNoIndirectInput,<br>
> -                                          options->EmitNoIndirectOutput,<br>
> -                                          options->EmitNoIndirectTemp,<br>
> -                                          options->EmitNoIndirectUniform);<br>
> -<br>
> -   if (unlikely(brw->perf_debug && lowered_variable_indexing)) {<br>
> -      perf_debug("Unsupported form of variable indexing in %s; falling "<br>
> -                 "back to very inefficient code generation\n",<br>
> -                 _mesa_shader_stage_to_abbrev(shader->Stage));<br>
> +   if (brw->gen < 7) {<br>
> +      bool lowered_variable_indexing =<br>
> +         lower_variable_index_to_cond_assign((gl_shader_stage)stage,<br>
> +                                             shader->ir,<br>
> +                                             options->EmitNoIndirectInput,<br>
> +                                             options->EmitNoIndirectOutput,<br>
> +                                             options->EmitNoIndirectTemp,<br>
> +                                             options->EmitNoIndirectUniform);<br>
> +<br>
> +      if (unlikely(brw->perf_debug && lowered_variable_indexing)) {<br>
> +         perf_debug("Unsupported form of variable indexing in %s; falling "<br>
> +                    "back to very inefficient code generation\n",<br>
> +                    _mesa_shader_stage_to_abbrev(shader->Stage));<br>
> +      }<br>
>     }<br>
><br>
>     bool progress;<br>
> diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c<br>
> index e8dafae..af646ed 100644<br>
> --- a/src/mesa/drivers/dri/i965/brw_nir.c<br>
> +++ b/src/mesa/drivers/dri/i965/brw_nir.c<br>
> @@ -453,6 +453,18 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)<br>
>     /* Lower a bunch of stuff */<br>
>     OPT_V(nir_lower_var_copies);<br>
><br>
> +   if (compiler->devinfo->gen > 6) {</p>
<p dir="ltr">I think you want "> 7" here</p>
<p dir="ltr">> +      nir_variable_mode indirect_mask = 0;<br>
> +      if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectInput)<br>
> +         indirect_mask |= nir_var_shader_in;<br>
> +      if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectOutput)<br>
> +         indirect_mask |= nir_var_shader_out;<br>
> +      if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectTemp)<br>
> +         indirect_mask |= nir_var_local;<br>
> +<br>
> +      nir_lower_indirect_derefs(nir, indirect_mask);<br>
> +   }<br>
> +<br>
>     /* Get rid of split copies */<br>
>     nir = nir_optimize(nir, is_scalar);<br>
><br>
> --<br>
> 2.7.4<br>
><br>
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