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<h1 style="font-size: 150%;font-weight:normal; color:#078DC7;"><a href="https://ci.appveyor.com/project/jrfonseca-fdo/mesa/build/2239" style="color:#078DC7;">Build mesa 2239 completed</a></h1>
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Commit <a href="">36f0f03182</a> by <a href="mailto:eric@anholt.net">Eric Anholt</a> on 9/7/2016 2:45 AM:
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<span style="font-size: 110%;color:#222;">nir: Allow opt_peephole_sel to be more aggressive in flattening IFs.\n\nVC4 was running into a major performance regression from enabling control\nflow in the glmark2 conditionals test, because of short if statements\ncontaining an ffract.\n\nThis pass seems like it was was trying to ensure that we only flattened\nIFs that should be entirely a win by guaranteeing that there would be\nfewer bcsels than there were MOVs otherwise. However, if the number of\nALU ops is small, we can avoid the overhead of branching (which itself\ncosts cycles) and still get a win, even if it means moving real\ninstructions out of the THEN/ELSE blocks.\n\nFor now, just turn on aggressive flattening on vc4. i965 will need some\ntuning to avoid regressions. It does looks like this may be useful to\nreplace freedreno code.\n\nImproves glmark2 -b conditionals:fragment-steps=5:vertex-steps=0 from 47\nfps to 95 fps on vc4.\n\nvc4 shader-db:\ntotal instructions in shared programs: 101282 -> 99543 (-1.72%)\ninstructions in affected programs: 17365 -> 15626 (-10.01%)\ntotal uniforms in shared programs: 31295 -> 31172 (-0.39%)\nuniforms in affected programs: 3580 -> 3457 (-3.44%)\ntotal estimated cycles in shared programs: 225182 -> 223746 (-0.64%)\nestimated cycles in affected programs: 26085 -> 24649 (-5.51%)\n\nv2: Update shader-db output.\n\nReviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)</span>
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