<div dir="ltr">Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br><div><div class="gmail_extra"><br><div class="gmail_quote">On Sat, Oct 8, 2016 at 1:15 AM, Randy Xu <span dir="ltr"><<a href="mailto:randy.xu@intel.com" target="_blank">randy.xu@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: "Xu,Randy" <<a href="mailto:randy.xu@intel.com">randy.xu@intel.com</a>><br>
<span class=""><br>
Add the miptree level/slice x/y_offset when count the surface offset<br>
in brw_emit_surface_state. The surface offset has two parts, one is<br>
from mt->offset, which should be 32 aligned in width/height for tiled<br>
buffer; another is from mt->level[current_level].<wbr>slice[current_slice].<br>
x/y_offset.<br>
<br>
This fix will solve 12 deqp failure<br>
dEQP-EGL.functional.image.<wbr>create.gles2_cubemap_negative_<wbr>*_texture<br>
<br>
Signed-off-by: Xu,Randy <<a href="mailto:randy.xu@intel.com">randy.xu@intel.com</a>><br>
---<br>
</span> src/mesa/drivers/dri/i965/brw_<wbr>wm_surface_state.c | 4 +++-<br>
 1 file changed, 3 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
index 61a4b94..d727526 100644<br>
<span class="">--- a/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_wm_surface_state.c<br>
@@ -85,7 +85,8 @@ brw_emit_surface_state(struct brw_context *brw,<br>
                        unsigned read_domains, unsigned write_domains)<br>
 {<br>
    const struct surface_state_info ss_info = surface_state_infos[brw->gen];<br>
-   uint32_t tile_x = 0, tile_y = 0;<br>
+   uint32_t tile_x = mt->level[0].slice[0].x_<wbr>offset;<br>
+   uint32_t tile_y = mt->level[0].slice[0].y_<wbr>offset;<br>
</span><span class="">    uint32_t offset = mt->offset;<br>
<br>
    struct isl_surf surf;<br>
</span>@@ -108,6 +109,7 @@ brw_emit_surface_state(struct brw_context *brw,<br>
<span class="im HOEnZb">        */<br>
       assert(brw->has_surface_tile_<wbr>offset);<br>
       assert(view.levels == 1 && view.array_len == 1);<br>
+      assert(tile_x == 0 && tile_y == 0);<br>
<br>
       offset += intel_miptree_get_tile_<wbr>offsets(mt, view.base_level,<br>
                                                view.base_array_layer,<br>
</span><div class="HOEnZb"><div class="h5">--<br>
2.7.4<br>
<br>
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</div></div></blockquote></div><br></div></div></div>