<p dir="ltr"></p>
<p dir="ltr">On Oct 24, 2016 2:58 AM, "Lionel Landwerlin" <<a href="mailto:lionel.g.landwerlin@intel.com">lionel.g.landwerlin@intel.com</a>> wrote:<br>
><br>
> Reviewed-by: Lionel Landwerlin <<a href="mailto:lionel.g.landwerlin@intel.com">lionel.g.landwerlin@intel.com</a>><br>
><br>
> Would adding the single register for gen6 makes sense?</p>
<p dir="ltr">It's not needed for this series but it wouldn't hurt.  I'll add it to the patch.</p>
<p dir="ltr">> On 22/10/16 18:50, Jason Ekstrand wrote:<br>
>><br>
>> ---<br>
>>   src/intel/genxml/gen7.xml  | 16 ++++++++++++++++<br>
>>   src/intel/genxml/gen75.xml | 16 ++++++++++++++++<br>
>>   src/intel/genxml/gen8.xml  | 16 ++++++++++++++++<br>
>>   src/intel/genxml/gen9.xml  | 16 ++++++++++++++++<br>
>>   4 files changed, 64 insertions(+)<br>
>><br>
>> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml<br>
>> index a950603..8461bd0 100644<br>
>> --- a/src/intel/genxml/gen7.xml<br>
>> +++ b/src/intel/genxml/gen7.xml<br>
>> @@ -2555,4 +2555,20 @@<br>
>>       <field name="T Low Bandwidth" start="21" end="21" type="uint"/><br>
>>     </register><br>
>>   +  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET3" length="1" num="0x528c"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>>   </genxml><br>
>> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml<br>
>> index 2c522d5..168c5cc 100644<br>
>> --- a/src/intel/genxml/gen75.xml<br>
>> +++ b/src/intel/genxml/gen75.xml<br>
>> @@ -2971,4 +2971,20 @@<br>
>>       <field name="L3 Atomic Disable Mask" start="22" end="22" type="uint"/><br>
>>     </register><br>
>>   +  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET3" length="1" num="0x528c"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>>   </genxml><br>
>> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml<br>
>> index 73c9265..07672ba 100644<br>
>> --- a/src/intel/genxml/gen8.xml<br>
>> +++ b/src/intel/genxml/gen8.xml<br>
>> @@ -3175,4 +3175,20 @@<br>
>>       <field name="All Allocation" start="25" end="31" type="uint"/><br>
>>     </register><br>
>>   +  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET3" length="1" num="0x528c"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>>   </genxml><br>
>> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml<br>
>> index 0dfce3f..3ddf63d 100644<br>
>> --- a/src/intel/genxml/gen9.xml<br>
>> +++ b/src/intel/genxml/gen9.xml<br>
>> @@ -3449,4 +3449,20 @@<br>
>>       <field name="All Allocation" start="25" end="31" type="uint"/><br>
>>     </register><br>
>>   +  <register name="SO_WRITE_OFFSET0" length="1" num="0x5280"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET1" length="1" num="0x5284"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET2" length="1" num="0x5288"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>> +  <register name="SO_WRITE_OFFSET3" length="1" num="0x528c"><br>
>> +    <field name="Write Offset" start="2" end="31" type="offset"/><br>
>> +  </register><br>
>> +<br>
>>   </genxml><br>
><br>
><br>
></p>