<div dir="ltr"> <div class="gmail_extra"> <div class="gmail_quote">On Tue, Nov 1, 2016 at 2:01 AM, Pohjolainen, Topi <<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">On Tue, Nov 01, 2016 at 07:24:50AM +0200, Pohjolainen, Topi wrote: > On Mon, Oct 31, 2016 at 02:51:06PM -0700, Jason Ekstrand wrote: > > On Mon, Oct 31, 2016 at 2:38 PM, Jason Ekstrand > > <[1]<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>> wrote: > > > > On Tue, Oct 11, 2016 at 12:26 PM, Topi Pohjolainen > > <[2]<a href="mailto:topi.pohjolainen@gmail.com">topi.pohjolainen@gmail.com</a>> wrote: > > > > From: Ben Widawsky <[3]<a href="mailto:ben@bwidawsk.net">ben@bwidawsk.net</a>> > > Signed-off-by: Ben Widawsky <[4]<a href="mailto:benjamin.widawsky@intel.com">benjamin.widawsky@intel.com</a>> > > --- > > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 51 > > ++++++++++++++++++--------- > > 1 file changed, 34 insertions(+), 17 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > > index f51392f..a41a654 100644 > > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > > @@ -224,33 +224,50 @@ intel_miptree_supports_non_msr > > t_fast_clear(struct brw_context *brw, > > return false; > > } > > + /* Handle the hardware restrictions... > > + * > > + * All GENs have the following restriction: "MCS buffer for > > non-MSRT is > > + * supported only for RT formats 32bpp, 64bpp, and 128bpp." > > + * > > + * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color > > Clear of > > + * Non-MultiSampler Render Target Restrictions) Support is for > > non-mip-mapped > > + * and non-array surface types only. > > + * > > + * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color > > Clear of > > + * Non-MultiSampler Render Target Restriction). Mip-mapped and > > arrayed > > + * surfaces are supported with MCS buffer layout with these > > alignments in the > > + * RT space: Horizontal Alignment = 256 and Vertical Alignment = > > 128. > > + * > > + * Skylake and above (docs are currently unpublished) are > > similar to BDW with > > > > Heh... Old patch. We should put in the real PRM citation. > > Do you have one specifically in mind? I haven't found any other piece > directly telling that arrayed and mipmapped is supported. </div></div>I think I understood what you meant, you were referring to the SKL part which should be: * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed * surfaces are supported with MCS buffer layout with these alignments in * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64. </blockquote></div> </div><div class="gmail_extra">Yes, that would be the one </div></div>