<div dir="ltr">I'm not sure how I feel about this one.  It seems like it would almost be easier to just pick one convention or the other for NIR and adjust one of the drivers accordingly.  I don't know that I have a huge preference which convention we choose.  I guess the Vulkan convention matches our hardware a bit better.  In either case, converting from one to the other should be a simple matter of building a remap table or a creative use of popcount.<br><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Nov 25, 2016 at 12:52 AM, Juan A. Suarez Romero <span dir="ltr"><<a href="mailto:jasuarez@igalia.com" target="_blank">jasuarez@igalia.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">One difference between OpenGL and Vulkan regarding 64-bit vertex<br>
attribute types is that dvec3 and dvec4 consumes just one location in<br>
OpenGL, while in Vulkan it consumes two locations.<br>
<br>
Thus, in OpenGL for each dvec3/dvec4 vertex attrib we mark just one bit<br>
in our internal inputs_read bitmap (and also the corresponding bit in<br>
double_inputs_read bitmap) while in Vulkan we mark two consecutive bits<br>
in both bitmaps.<br>
<br>
This is handled with a nir option called "dvec3_consumes_two_locations"<wbr>,<br>
which is set to True for Vulkan code. And all the computation regarding<br>
emitting vertices as well as the mapping between attributes and physical<br>
registers use this option to correctly do the work.<br>
---<br>
 src/amd/vulkan/radv_pipeline.c               |  1 +<br>
 src/compiler/nir/nir.h                       |  5 +++<br>
 src/compiler/nir/nir_gather_<wbr>info.c           |  6 +--<br>
 src/gallium/drivers/freedreno/<wbr>ir3/ir3_nir.c  |  1 +<br>
 src/intel/vulkan/anv_device.c                |  2 +-<br>
 src/intel/vulkan/genX_<wbr>pipeline.c             | 62 +++++++++++++++++-----------<br>
 src/mesa/drivers/dri/i965/brw_<wbr>compiler.c     | 23 ++++++++++-<br>
 src/mesa/drivers/dri/i965/brw_<wbr>compiler.h     |  2 +-<br>
 src/mesa/drivers/dri/i965/brw_<wbr>fs_visitor.cpp | 14 +++++--<br>
 src/mesa/drivers/dri/i965/brw_<wbr>nir.c          | 18 +++++---<br>
 src/mesa/drivers/dri/i965/brw_<wbr>vec4.cpp       | 13 ++++--<br>
 src/mesa/drivers/dri/i965/<wbr>intel_screen.c     |  3 +-<br>
 12 files changed, 105 insertions(+), 45 deletions(-)<br>
<br>
diff --git a/src/amd/vulkan/radv_<wbr>pipeline.c b/src/amd/vulkan/radv_<wbr>pipeline.c<br>
index ee5d812..90d4650 100644<br>
--- a/src/amd/vulkan/radv_<wbr>pipeline.c<br>
+++ b/src/amd/vulkan/radv_<wbr>pipeline.c<br>
@@ -59,6 +59,7 @@ static const struct nir_shader_compiler_options nir_options = {<br>
        .lower_unpack_unorm_4x8 = true,<br>
        .lower_extract_byte = true,<br>
        .lower_extract_word = true,<br>
+       .dvec3_consumes_two_locations = true,<br>
 };<br>
<br>
 VkResult radv_CreateShaderModule(<br>
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h<br>
index 1679d89..0fc8f39 100644<br>
--- a/src/compiler/nir/nir.h<br>
+++ b/src/compiler/nir/nir.h<br>
@@ -1794,6 +1794,11 @@ typedef struct nir_shader_compiler_options {<br>
     * information must be inferred from the list of input nir_variables.<br>
     */<br>
    bool use_interpolated_input_<wbr>intrinsics;<br>
+<br>
+   /**<br>
+    * In Vulkan, a dvec3/dvec4 consumes two locations instead just one.<br>
+    */<br>
+   bool dvec3_consumes_two_locations;<br>
 } nir_shader_compiler_options;<br>
<br>
 typedef struct nir_shader {<br>
diff --git a/src/compiler/nir/nir_gather_<wbr>info.c b/src/compiler/nir/nir_gather_<wbr>info.c<br>
index 07c9949..8c80671 100644<br>
--- a/src/compiler/nir/nir_gather_<wbr>info.c<br>
+++ b/src/compiler/nir/nir_gather_<wbr>info.c<br>
@@ -96,7 +96,7 @@ mark_whole_variable(nir_shader *shader, nir_variable *var)<br>
<br>
    const unsigned slots =<br>
       var->data.compact ? DIV_ROUND_UP(glsl_get_length(<wbr>type), 4)<br>
-                        : glsl_count_attribute_slots(<wbr>type, is_vertex_input);<br>
+                        : glsl_count_attribute_slots(<wbr>type, is_vertex_input && !shader->options->dvec3_<wbr>consumes_two_locations);<br></blockquote><div><br></div><div>This makes no sense, why are we passing is_vertex_input && !dvec3_consumes_two_locations to an argument labled is_vertex_input?<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
    set_io_mask(shader, var, 0, slots);<br>
 }<br>
@@ -168,7 +168,7 @@ try_mask_partial_io(nir_shader *shader, nir_deref_var *deref)<br>
        var->data.mode == nir_var_shader_in)<br>
       is_vertex_input = true;<br>
<br>
-   unsigned offset = get_io_offset(deref, is_vertex_input);<br>
+   unsigned offset = get_io_offset(deref, is_vertex_input && !shader->options->dvec3_<wbr>consumes_two_locations);<br></blockquote><div><br></div><div>Same here<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
    if (offset == -1)<br>
       return false;<br>
<br>
@@ -184,7 +184,7 @@ try_mask_partial_io(nir_shader *shader, nir_deref_var *deref)<br>
    }<br>
<br>
    /* double element width for double types that takes two slots */<br>
-   if (!is_vertex_input &&<br>
+   if ((!is_vertex_input || shader->options->dvec3_<wbr>consumes_two_locations) &&<br>
        glsl_type_is_dual_slot(glsl_<wbr>without_array(type))) {<br></blockquote><div><br></div><div>This makes a bit more sense but I'm still not quite seeing it.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
       elem_width *= 2;<br>
    }<br>
diff --git a/src/gallium/drivers/<wbr>freedreno/ir3/ir3_nir.c b/src/gallium/drivers/<wbr>freedreno/ir3/ir3_nir.c<br>
index 2d86a52..5c5c9ad 100644<br>
--- a/src/gallium/drivers/<wbr>freedreno/ir3/ir3_nir.c<br>
+++ b/src/gallium/drivers/<wbr>freedreno/ir3/ir3_nir.c<br>
@@ -50,6 +50,7 @@ static const nir_shader_compiler_options options = {<br>
                .vertex_id_zero_based = true,<br>
                .lower_extract_byte = true,<br>
                .lower_extract_word = true,<br>
+               .dvec3_consumes_two_locations = false,<br>
 };<br>
<br>
 struct nir_shader *<br>
diff --git a/src/intel/vulkan/anv_device.<wbr>c b/src/intel/vulkan/anv_device.<wbr>c<br>
index 2c8ac49..725848f 100644<br>
--- a/src/intel/vulkan/anv_device.<wbr>c<br>
+++ b/src/intel/vulkan/anv_device.<wbr>c<br>
@@ -167,7 +167,7 @@ anv_physical_device_init(<wbr>struct anv_physical_device *device,<br>
<br>
    brw_process_intel_debug_<wbr>variable();<br>
<br>
-   device->compiler = brw_compiler_create(NULL, &device->info);<br>
+   device->compiler = brw_compiler_create(NULL, &device->info, true);<br>
    if (device->compiler == NULL) {<br>
       result = vk_error(VK_ERROR_OUT_OF_HOST_<wbr>MEMORY);<br>
       goto fail;<br>
diff --git a/src/intel/vulkan/genX_<wbr>pipeline.c b/src/intel/vulkan/genX_<wbr>pipeline.c<br>
index cb164ad..97c40b8 100644<br>
--- a/src/intel/vulkan/genX_<wbr>pipeline.c<br>
+++ b/src/intel/vulkan/genX_<wbr>pipeline.c<br>
@@ -33,26 +33,33 @@<br>
 static uint32_t<br>
 vertex_element_comp_control(<wbr>enum isl_format format, unsigned comp)<br>
 {<br>
-   uint8_t bits;<br>
    switch (comp) {<br>
-   case 0: bits = isl_format_layouts[format].<wbr>channels.r.bits; break;<br>
-   case 1: bits = isl_format_layouts[format].<wbr>channels.g.bits; break;<br>
-   case 2: bits = isl_format_layouts[format].<wbr>channels.b.bits; break;<br>
-   case 3: bits = isl_format_layouts[format].<wbr>channels.a.bits; break;<br>
-   default: unreachable("Invalid component");<br>
-   }<br>
-<br>
-   if (bits) {<br>
-      return VFCOMP_STORE_SRC;<br>
-   } else if (comp < 3) {<br>
-      return VFCOMP_STORE_0;<br>
-   } else if (isl_format_layouts[format].<wbr>channels.r.type == ISL_UINT ||<br>
-            isl_format_layouts[format].<wbr>channels.r.type == ISL_SINT) {<br>
-      assert(comp == 3);<br>
-      return VFCOMP_STORE_1_INT;<br>
-   } else {<br>
-      assert(comp == 3);<br>
-      return VFCOMP_STORE_1_FP;<br>
+   case 0:<br>
+      return isl_format_layouts[format].<wbr>channels.r.bits ?<br>
+         VFCOMP_STORE_SRC : VFCOMP_STORE_0;<br>
+   case 1:<br>
+      return isl_format_layouts[format].<wbr>channels.g.bits ?<br>
+         VFCOMP_STORE_SRC : VFCOMP_STORE_0;<br>
+   case 2:<br>
+      return isl_format_layouts[format].<wbr>channels.b.bits ?<br>
+         VFCOMP_STORE_SRC : ((isl_format_layouts[format].<wbr>channels.r.type == ISL_RAW) ?<br>
+                             VFCOMP_NOSTORE : VFCOMP_STORE_0);<br>
+   case 3:<br>
+      if (isl_format_layouts[format].<wbr>channels.a.bits)<br>
+         return VFCOMP_STORE_SRC;<br>
+      else<br>
+         switch (isl_format_layouts[format].<wbr>channels.r.type) {<br>
+         case ISL_RAW:<br>
+            return isl_format_layouts[format].<wbr>channels.b.bits ?<br>
+               VFCOMP_STORE_0 : VFCOMP_NOSTORE;<br>
+         case ISL_UINT:<br>
+         case ISL_SINT:<br>
+            return VFCOMP_STORE_1_INT;<br>
+         default:<br>
+            return VFCOMP_STORE_1_FP;<br>
+         }<br>
+   default:<br>
+      unreachable("Invalid component");<br>
    }<br>
 }<br>
<br>
@@ -64,8 +71,10 @@ emit_vertex_input(struct anv_pipeline *pipeline,<br>
<br>
    /* Pull inputs_read out of the VS prog data */<br>
    const uint64_t inputs_read = vs_prog_data->inputs_read;<br>
+   const uint64_t double_inputs_read = vs_prog_data->double_inputs_<wbr>read;<br>
    assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);<br>
    const uint32_t elements = inputs_read >> VERT_ATTRIB_GENERIC0;<br>
+   const uint32_t elements_double = double_inputs_read >> VERT_ATTRIB_GENERIC0;<br>
<br>
 #if GEN_GEN >= 8<br>
    /* On BDW+, we only need to allocate space for base ids.  Setting up<br>
@@ -83,13 +92,16 @@ emit_vertex_input(struct anv_pipeline *pipeline,<br>
                                 vs_prog_data->uses_<wbr>baseinstance;<br>
 #endif<br>
<br>
-   uint32_t elem_count = __builtin_popcount(elements) + needs_svgs_elem;<br>
-   if (elem_count == 0)<br>
+   uint32_t elem_count =<br>
+      __builtin_popcount(elements) - DIV_ROUND_UP(__builtin_<wbr>popcount(elements_double), 2);<br>
+<br>
+   uint32_t total_elems = elem_count + needs_svgs_elem;<br>
+   if (total_elems == 0)<br>
       return;<br>
<br>
    uint32_t *p;<br>
<br>
-   const uint32_t num_dwords = 1 + elem_count * 2;<br>
+   const uint32_t num_dwords = 1 + total_elems * 2;<br>
    p = anv_batch_emitn(&pipeline-><wbr>batch, num_dwords,<br>
                        GENX(3DSTATE_VERTEX_ELEMENTS))<wbr>;<br>
    memset(p + 1, 0, (num_dwords - 1) * 4);<br>
@@ -107,7 +119,9 @@ emit_vertex_input(struct anv_pipeline *pipeline,<br>
       if ((elements & (1 << desc->location)) == 0)<br>
          continue; /* Binding unused */<br>
<br>
-      uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));<br>
+      uint32_t slot =<br>
+         __builtin_popcount(elements & ((1 << desc->location) - 1)) -<br>
+         DIV_ROUND_UP(__builtin_<wbr>popcount(elements_double & ((1 << desc->location) - 1)), 2);<br>
<br>
       struct GENX(VERTEX_ELEMENT_STATE) element = {<br>
          .VertexBufferIndex = desc->binding,<br>
@@ -137,7 +151,7 @@ emit_vertex_input(struct anv_pipeline *pipeline,<br>
 #endif<br>
    }<br>
<br>
-   const uint32_t id_slot = __builtin_popcount(elements);<br>
+   const uint32_t id_slot = elem_count;<br>
    if (needs_svgs_elem) {<br>
       /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:<br>
        *    "Within a VERTEX_ELEMENT_STATE structure, if a Component<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_compiler.c b/src/mesa/drivers/dri/i965/<wbr>brw_compiler.c<br>
index 1aa72bc..b9eceeb 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_compiler.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_compiler.c<br>
@@ -55,6 +55,22 @@ static const struct nir_shader_compiler_options scalar_nir_options = {<br>
    .lower_unpack_snorm_4x8 = true,<br>
    .lower_unpack_unorm_2x16 = true,<br>
    .lower_unpack_unorm_4x8 = true,<br>
+   .dvec3_consumes_two_locations = false,<br>
+};<br>
+<br>
+static const struct nir_shader_compiler_options vulkan_scalar_nir_options = {<br>
+   COMMON_OPTIONS,<br>
+   .lower_pack_half_2x16 = true,<br>
+   .lower_pack_snorm_2x16 = true,<br>
+   .lower_pack_snorm_4x8 = true,<br>
+   .lower_pack_unorm_2x16 = true,<br>
+   .lower_pack_unorm_4x8 = true,<br>
+   .lower_unpack_half_2x16 = true,<br>
+   .lower_unpack_snorm_2x16 = true,<br>
+   .lower_unpack_snorm_4x8 = true,<br>
+   .lower_unpack_unorm_2x16 = true,<br>
+   .lower_unpack_unorm_4x8 = true,<br>
+   .dvec3_consumes_two_locations = true,<br>
 };<br>
<br>
 static const struct nir_shader_compiler_options vector_nir_options = {<br>
@@ -75,6 +91,7 @@ static const struct nir_shader_compiler_options vector_nir_options = {<br>
    .lower_unpack_unorm_2x16 = true,<br>
    .lower_extract_byte = true,<br>
    .lower_extract_word = true,<br>
+   .dvec3_consumes_two_locations = false,<br>
 };<br>
<br>
 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {<br>
@@ -92,10 +109,11 @@ static const struct nir_shader_compiler_options vector_nir_options_gen6 = {<br>
    .lower_unpack_unorm_2x16 = true,<br>
    .lower_extract_byte = true,<br>
    .lower_extract_word = true,<br>
+   .dvec3_consumes_two_locations = false,<br>
 };<br>
<br>
 struct brw_compiler *<br>
-brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)<br>
+brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo, bool is_vulkan)<br>
 {<br>
    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);<br>
<br>
@@ -138,7 +156,8 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)<br>
          compiler->glsl_compiler_<wbr>options[i].<wbr>EmitNoIndirectSampler = true;<br>
<br>
       if (is_scalar) {<br>
-         compiler->glsl_compiler_<wbr>options[i].NirOptions = &scalar_nir_options;<br>
+         compiler->glsl_compiler_<wbr>options[i].NirOptions = is_vulkan ? &vulkan_scalar_nir_options<br>
+                                                                   : &scalar_nir_options;<br>
       } else {<br>
          compiler->glsl_compiler_<wbr>options[i].NirOptions =<br>
             devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_compiler.h b/src/mesa/drivers/dri/i965/<wbr>brw_compiler.h<br>
index 65a7478..34df343 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_compiler.h<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_compiler.h<br>
@@ -760,7 +760,7 @@ DEFINE_PROG_DATA_DOWNCAST(sf)<br>
 /** @} */<br>
<br>
 struct brw_compiler *<br>
-brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo);<br>
+brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo, bool is_vulkan);<br>
<br>
 /**<br>
  * Compile a vertex shader.<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/<wbr>brw_fs_visitor.cpp<br>
index 14415bd..00c5bb4 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_fs_visitor.cpp<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_fs_visitor.cpp<br>
@@ -35,10 +35,16 @@ using namespace brw;<br>
 fs_reg *<br>
 fs_visitor::emit_vs_system_<wbr>value(int location)<br>
 {<br>
-   fs_reg *reg = new(this->mem_ctx)<br>
-      fs_reg(ATTR, 4 * (_mesa_bitcount_64(nir->info-><wbr>inputs_read) +<br>
-                        _mesa_bitcount_64(nir->info-><wbr>double_inputs_read)),<br>
-             BRW_REGISTER_TYPE_D);<br>
+   fs_reg *reg;<br>
+   if (nir->options->dvec3_consumes_<wbr>two_locations)<br>
+      reg = new(this->mem_ctx)<br>
+         fs_reg(ATTR, 4 * _mesa_bitcount_64(nir->info-><wbr>inputs_read),<br>
+                BRW_REGISTER_TYPE_D);<br>
+   else<br>
+      reg = new(this->mem_ctx)<br>
+         fs_reg(ATTR, 4 * (_mesa_bitcount_64(nir->info-><wbr>inputs_read) +<br>
+                           _mesa_bitcount_64(nir->info-><wbr>double_inputs_read)),<br>
+                BRW_REGISTER_TYPE_D);<br>
    struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(prog_data);<br>
<br>
    switch (location) {<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_nir.c b/src/mesa/drivers/dri/i965/<wbr>brw_nir.c<br>
index 763e3ec..daa22c6 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_nir.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_nir.c<br>
@@ -96,7 +96,7 @@ add_const_offset_to_base(nir_<wbr>shader *nir, nir_variable_mode mode)<br>
 }<br>
<br>
 static bool<br>
-remap_vs_attrs(nir_block *block, shader_info *nir_info)<br>
+remap_vs_attrs(nir_block *block, nir_shader *nir)<br>
 {<br>
    nir_foreach_instr(instr, block) {<br>
       if (instr->type != nir_instr_type_intrinsic)<br>
@@ -111,10 +111,13 @@ remap_vs_attrs(nir_block *block, shader_info *nir_info)<br>
           * before it and counting the bits.<br>
           */<br>
          int attr = intrin->const_index[0];<br>
-         int slot = _mesa_bitcount_64(nir_info-><wbr>inputs_read &<br>
+         int slot = _mesa_bitcount_64(nir->info-><wbr>inputs_read &<br>
+                                      BITFIELD64_MASK(attr));<br>
+<br>
+         int dslot = 0;<br>
+         if (!nir->options->dvec3_<wbr>consumes_two_locations)<br>
+            dslot = _mesa_bitcount_64(nir->info-><wbr>double_inputs_read &<br>
                                       BITFIELD64_MASK(attr));<br>
-         int dslot = _mesa_bitcount_64(nir_info-><wbr>double_inputs_read &<br>
-                                       BITFIELD64_MASK(attr));<br>
          intrin->const_index[0] = 4 * (slot + dslot);<br>
       }<br>
    }<br>
@@ -204,7 +207,10 @@ brw_nir_lower_vs_inputs(nir_<wbr>shader *nir,<br>
     * loaded as one vec4 or dvec4 per element (or matrix column), depending on<br>
     * whether it is a double-precision type or not.<br>
     */<br>
-   nir_lower_io(nir, nir_var_shader_in, type_size_vs_input, 0);<br>
+   nir_lower_io(nir,<br>
+                nir_var_shader_in,<br>
+                nir->options->dvec3_consumes_<wbr>two_locations ? type_size_vec4 : type_size_vs_input,<br>
+                0);<br>
<br>
    /* This pass needs actual constants */<br>
    nir_opt_constant_folding(nir);<br>
@@ -220,7 +226,7 @@ brw_nir_lower_vs_inputs(nir_<wbr>shader *nir,<br>
       nir_foreach_function(function, nir) {<br>
          if (function->impl) {<br>
             nir_foreach_block(block, function->impl) {<br>
-               remap_vs_attrs(block, nir->info);<br>
+               remap_vs_attrs(block, nir);<br>
             }<br>
          }<br>
       }<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_vec4.cpp b/src/mesa/drivers/dri/i965/<wbr>brw_vec4.cpp<br>
index b9e592f..0aab97f 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_vec4.cpp<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_vec4.cpp<br>
@@ -2129,6 +2129,9 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,<br>
<br>
    unsigned nr_attributes = _mesa_bitcount_64(prog_data-><wbr>inputs_read);<br>
<br>
+   if (shader->options->dvec3_<wbr>consumes_two_locations)<br>
+      nr_attributes -= DIV_ROUND_UP(_mesa_bitcount_<wbr>64(prog_data->double_inputs_<wbr>read), 2);<br>
+<br>
    /* gl_VertexID and gl_InstanceID are system values, but arrive via an<br>
     * incoming vertex attribute.  So, add an extra slot.<br>
     */<br>
@@ -2146,9 +2149,13 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,<br>
       nr_attributes++;<br>
    }<br>
<br>
-   unsigned nr_attribute_slots =<br>
-      nr_attributes +<br>
-      _mesa_bitcount_64(shader-><wbr>info->double_inputs_read);<br>
+   unsigned nr_attribute_slots = nr_attributes;<br>
+   if (shader->options->dvec3_<wbr>consumes_two_locations)<br>
+      nr_attribute_slots +=<br>
+         DIV_ROUND_UP(_mesa_bitcount_<wbr>64(shader->info->double_<wbr>inputs_read), 2);<br>
+   else<br>
+      nr_attribute_slots +=<br>
+         _mesa_bitcount_64(shader-><wbr>info->double_inputs_read);<br>
<br>
    /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry<br>
     * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode.  Empirically, in<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>intel_screen.c b/src/mesa/drivers/dri/i965/<wbr>intel_screen.c<br>
index e1c3c19..c050f86 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>intel_screen.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>intel_screen.c<br>
@@ -1688,7 +1688,8 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)<br>
       ? screenExtensions : intelRobustScreenExtensions;<br>
<br>
    screen->compiler = brw_compiler_create(screen,<br>
-                                          &screen->devinfo);<br>
+                                          &screen->devinfo,<br>
+                                          false);<br>
    screen->compiler->shader_<wbr>debug_log = shader_debug_log_mesa;<br>
    screen->compiler->shader_perf_<wbr>log = shader_perf_log_mesa;<br>
    screen->program_id = 1;<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.7.4<br>
<br>
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</font></span></blockquote></div><br></div></div>