<div dir="ltr">Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jan 16, 2017 at 4:07 AM, Samuel Iglesias Gonsálvez <span dir="ltr"><<a href="mailto:siglesias@igalia.com" target="_blank">siglesias@igalia.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Reviewed-by: Samuel Iglesias Gonsálvez <<a href="mailto:siglesias@igalia.com">siglesias@igalia.com</a>><br>
<div class="HOEnZb"><div class="h5"><br>
On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote:<br>
> Only caller, brw_workaround_depthstencil_<wbr>alignment(), returns<br>
> early for gen6+.<br>
><br>
> While at it, reduce scope for brw_get_depthstencil_tile_<wbr>masks() as<br>
> well.<br>
><br>
> Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
> ---<br>
> src/mesa/drivers/dri/i965/<wbr>brw_context.h | 6 ------<br>
> src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c | 18 ++----------------<br>
> 2 files changed, 2 insertions(+), 22 deletions(-)<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
> b/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
> index ff3f861..4176853 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>brw_context.h<br>
> @@ -1279,12 +1279,6 @@ brw_meta_resolve_color(struct brw_context<br>
> *brw,<br>
> /*===========================<wbr>==============================<wbr>=========<br>
> ====<br>
> * brw_misc_state.c<br>
> */<br>
> -void brw_get_depthstencil_tile_<wbr>masks(struct intel_mipmap_tree<br>
> *depth_mt,<br>
> - <wbr> uint32_t depth_level,<br>
> - <wbr> uint32_t depth_layer,<br>
> - <wbr> struct intel_mipmap_tree<br>
> *stencil_mt,<br>
> - <wbr> uint32_t *out_tile_mask_x,<br>
> - <wbr> uint32_t *out_tile_mask_y);<br>
> void brw_workaround_depthstencil_<wbr>alignment(struct brw_context *brw,<br>
> <wbr> GLbitfield clear_mask);<br>
> <br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
> b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
> index 40a8d07..616c0df 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>brw_misc_state.c<br>
> @@ -165,7 +165,7 @@ brw_depthbuffer_format(struct brw_context *brw)<br>
> * packet. If the 3 buffers don't agree on the drawing offset ANDed<br>
> with this<br>
> * mask, then we're in trouble.<br>
> */<br>
> -void<br>
> +static void<br>
> brw_get_depthstencil_tile_<wbr>masks(struct intel_mipmap_tree *depth_mt,<br>
> <wbr> uint32_t depth_level,<br>
> <wbr> uint32_t depth_layer,<br>
> @@ -179,21 +179,7 @@ brw_get_depthstencil_tile_<wbr>masks(struct<br>
> intel_mipmap_tree *depth_mt,<br>
> intel_get_tile_masks(<wbr>depth_mt->tiling, depth_mt->tr_mode,<br>
> <wbr>depth_mt->cpp,<br>
> &<wbr>tile_mask_x, &tile_mask_y);<br>
> -<br>
> - if (intel_miptree_level_has_hiz(<wbr>depth_mt, depth_level)) {<br>
> - uint32_t hiz_tile_mask_x, hiz_tile_mask_y;<br>
> - intel_get_tile_<wbr>masks(depth_mt->hiz_buf->mt-><wbr>tiling,<br>
> - <wbr> depth_mt->hiz_buf->mt->tr_<wbr>mode,<br>
> - <wbr> depth_mt->hiz_buf->mt->cpp,<br>
> - <wbr> &hiz_tile_mask_x,<br>
> - <wbr> &hiz_tile_mask_y);<br>
> -<br>
> - /* Each HiZ row represents 2 rows of pixels */<br>
> - hiz_tile_mask_y = hiz_tile_mask_y << 1 | 1;<br>
> -<br>
> - tile_mask_x |= hiz_tile_mask_x;<br>
> - tile_mask_y |= hiz_tile_mask_y;<br>
> - }<br>
> + assert(!intel_miptree_<wbr>level_has_hiz(depth_mt, depth_level));<br>
> }<br>
> <br>
> if (stencil_mt) {<br>
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