<div dir="auto"><div><div class="gmail_extra"><div class="gmail_quote">On Jan 18, 2017 2:22 AM, "Topi Pohjolainen" <<a href="mailto:topi.pohjolainen@gmail.com">topi.pohjolainen@gmail.com</a>> wrote:<br type="attribution"><blockquote class="quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="quoted-text">Current blorp logic issues unconditional "flush everything"<br>
(see brw_emit_mi_flush()) after each render. For example, all<br>
blits issue this unconditionally which shouldn't be needed if<br>
they set render cache properly os that subsequent renders do<br>
necessary flushing before drawing.<br>
<br>
In case of piglit:<br>
<br>
ext_framebuffer_multisample-<wbr>accuracy all_samples depth_draw small<br>
<br>
intel_hiz_exec() is always preceded by blorb blit and the<br>
unconditional flush looks to hide the lack of stall and flushes<br>
in depth clears. By removing the brw_emit_mi_flush() I get gpu<br>
hangs.<br>
<br>
This patch adds the stalls and flushes mandated by the spec<br>
and gets rid of those hangs.<br>
<br>
</div>v2 (Jason, Ken): Document the rational for separating<br>
depth cache flush and stall on Gen7.<br>
<div class="quoted-text"><br>
Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
</div> src/mesa/drivers/dri/i965/brw_<wbr>clear.c | 49 +++++++++++++++++++++++-----<br>
src/mesa/drivers/dri/i965/<wbr>gen8_depth_state.c | 16 +++++++++<br>
2 files changed, 57 insertions(+), 8 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_clear.c b/src/mesa/drivers/dri/i965/<wbr>brw_clear.c<br>
index 488732c..7fcde6c 100644<br>
<div class="quoted-text">--- a/src/mesa/drivers/dri/i965/<wbr>brw_clear.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_clear.c<br>
@@ -36,6 +36,7 @@<br>
<br>
#include "brw_context.h"<br>
#include "brw_blorp.h"<br>
+#include "brw_defines.h"<br>
<br>
#define FILE_DEBUG_FLAG DEBUG_BLIT<br>
<br>
</div>@@ -174,14 +175,46 @@ brw_fast_clear_depth(struct gl_context *ctx)<br>
<div class="quoted-text"> mt->depth_clear_value = depth_clear_value;<br>
}<br>
<br>
- /* From the Sandy Bridge PRM, volume 2 part 1, page 313:<br>
- *<br>
- * "If other rendering operations have preceded this clear, a<br>
- * PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled<br>
- * must be issued before the rectangle primitive used for the depth<br>
- * buffer clear operation.<br>
- */<br>
- brw_emit_mi_flush(brw);<br>
+ if (brw->gen == 6) {<br>
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 313:<br>
+ *<br>
+ * "If other rendering operations have preceded this clear, a<br>
+ * PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled<br>
+ * must be issued before the rectangle primitive used for the depth<br>
+ * buffer clear operation.<br>
+ */<br>
+ brw_emit_pipe_control_flush(<wbr>brw,<br>
+ PIPE_CONTROL_RENDER_TARGET_<wbr>FLUSH |<br>
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |<br>
+ PIPE_CONTROL_CS_STALL);<br>
+ } else if (brw->gen >= 7) {<br>
+ /*<br>
</div>+ * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":<br>
<div class="quoted-text">+ *<br>
+ * If other rendering operations have preceded this clear, a<br>
+ * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit<br>
+ * enabled must be issued before the rectangle primitive used for the<br>
+ * depth buffer clear operation.<br>
+ *<br>
+ * Same applies for Gen8 and Gen9.<br>
+ *<br>
</div>+ * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1 PIPE_CONTROL,<br>
+ * Depth Cache Flush Enable:<br>
+ *<br>
+ * This bit must not be set when Depth Stall Enable bit is set in<br>
+ * this packet.<br>
+ *<br>
+ * This is confirmed to hold for real, HSW gets immediate gpu hangs.<br>
+ *<br>
+ * Therefore issue two pipe control flushes, one for cache flush and<br>
+ * another for depth stall.<br>
<div class="elided-text">+ */<br></div></blockquote></div></div></div><div dir="auto"><br></div><div dir="auto">Makes more sense, thanks! All 4 are</div><div dir="auto"><span style="font-family:sans-serif"><br></span></div><div dir="auto"><span style="font-family:sans-serif">Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>></span></div><div dir="auto"><span style="font-family:sans-serif"><br></span></div><div dir="auto"><span style="font-family:sans-serif">That said... My intuition about flushing indicates that you may be able to get away with just doing a depth stall and then a flush without the CS stall. That would potentially let is avoid the CS stall. I could be completely wrong though and I think what you did is probably the safest way to go.</span></div><div dir="auto"><br></div><div dir="auto"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="elided-text">
+ brw_emit_pipe_control_flush(<wbr>brw,<br>
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |<br>
+ PIPE_CONTROL_CS_STALL);<br>
+<br>
+ brw_emit_pipe_control_flush(<wbr>brw, PIPE_CONTROL_DEPTH_STALL);<br>
+ }<br>
<br>
if (fb->MaxNumLayers > 0) {<br>
for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>gen8_depth_state.c b/src/mesa/drivers/dri/i965/<wbr>gen8_depth_state.c<br>
index 14689f4..ec29669 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>gen8_depth_state.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>gen8_depth_state.c<br>
@@ -511,6 +511,22 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,<br>
OUT_BATCH(0);<br>
ADVANCE_BATCH();<br>
<br>
+ /*<br>
+ * From the Broadwell PRM, volume 7, "Depth Buffer Clear":<br>
+ *<br>
+ * Depth buffer clear pass using any of the methods (WM_STATE, 3DSTATE_WM<br>
+ * or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL command with<br>
+ * DEPTH_STALL bit and Depth FLUSH bits "set" before starting to render.<br>
+ * DepthStall and DepthFlush are not needed between consecutive depth<br>
+ * clear passes nor is it required if th e depth clear pass was done with<br>
+ * "full_surf_clear" bit set in the 3DSTATE_WM_HZ_OP.<br>
+ *<br>
+ * TODO: Such as the spec says, this could be conditional.<br>
+ */<br>
+ brw_emit_pipe_control_flush(<wbr>brw,<br>
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |<br>
+ PIPE_CONTROL_DEPTH_STALL);<br>
+<br>
/* Mark this buffer as needing a TC flush, as we've rendered to it. */<br>
brw_render_cache_set_add_bo(<wbr>brw, mt->bo);<br>
<br>
--<br>
2.5.5<br>
<br>
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</div></blockquote></div><br></div></div></div>