<div dir="auto"><div><div class="gmail_extra"><div class="gmail_quote">On Jan 18, 2017 1:47 PM, "Francisco Jerez" <<a href="mailto:currojerez@riseup.net">currojerez@riseup.net</a>> wrote:<br type="attribution"><blockquote class="quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="quoted-text">Topi Pohjolainen <<a href="mailto:topi.pohjolainen@gmail.com">topi.pohjolainen@gmail.com</a>> writes:<br>
<br>
> Blits do not need any special treatment as the target buffer<br>
> object is added to render cache just as one does for normal draw.<br>
> Color clears and resolves in turn require explicit "end of pipe<br>
> synchronization". It is not clear what this means exactly but the<br>
> assumption is that render cache flush with command stream stall<br>
> should be sufficient.<br>
><br>
<br>
</div>Don't the clear and resolve paths end up calling genX(blorp_exec), where<br>
you used the render cache mechanism to flush a superset of the caches<br>
flushed below?  Why do you need to synchronize and flush twice?</blockquote></div></div></div><div dir="auto"><br></div><div dir="auto">Thanks.  I recall having that same thought but apparently forgot it.  I think we may still bed the resolve flush (there are extra flushes required around resolves) but not the color clear flush.</div><div dir="auto"><br></div><div dir="auto"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="elided-text">
> Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
> ---<br>
>  src/mesa/drivers/dri/i965/brw_<wbr>blorp.c       | 22 ++++++++++++++++++++++<br>
>  src/mesa/drivers/dri/i965/<wbr>genX_blorp_exec.c |  5 -----<br>
>  2 files changed, 22 insertions(+), 5 deletions(-)<br>
><br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c b/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c<br>
> index 8d58616..845abe3 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c<br>
> @@ -908,6 +908,17 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,<br>
>        blorp_batch_finish(&batch);<br>
>     }<br>
><br>
> +   /*<br>
> +    * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":<br>
> +    *<br>
> +    *  Any transition from any value in {Clear, Render, Resolve} to a<br>
> +    *  different value in {Clear, Render, Resolve} requires end of pipe<br>
> +    *  synchronization.<br>
> +    */<br>
> +   brw_emit_pipe_control_flush(<wbr>brw,<br>
> +                               PIPE_CONTROL_RENDER_TARGET_<wbr>FLUSH |<br>
> +                               PIPE_CONTROL_CS_STALL);<br>
> +<br>
>     return true;<br>
>  }<br>
><br>
> @@ -975,6 +986,17 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,<br>
>                       brw_blorp_to_isl_format(brw, format, true),<br>
>                       resolve_op);<br>
>     blorp_batch_finish(&batch);<br>
> +<br>
> +   /*<br>
> +    * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":<br>
> +    *<br>
> +    *  Any transition from any value in {Clear, Render, Resolve} to a<br>
> +    *  different value in {Clear, Render, Resolve} requires end of pipe<br>
> +    *  synchronization.<br>
> +    */<br>
> +   brw_emit_pipe_control_flush(<wbr>brw,<br>
> +                               PIPE_CONTROL_RENDER_TARGET_<wbr>FLUSH |<br>
> +                               PIPE_CONTROL_CS_STALL);<br>
>  }<br>
><br>
>  static void<br>
> diff --git a/src/mesa/drivers/dri/i965/<wbr>genX_blorp_exec.c b/src/mesa/drivers/dri/i965/<wbr>genX_blorp_exec.c<br>
> index c0cbde5..2c53444 100644<br>
> --- a/src/mesa/drivers/dri/i965/<wbr>genX_blorp_exec.c<br>
> +++ b/src/mesa/drivers/dri/i965/<wbr>genX_blorp_exec.c<br>
> @@ -260,9 +260,4 @@ retry:<br>
>     brw->ib.type = -1;<br>
><br>
>     brw_render_cache_set_add_bo(<wbr>brw, params->dst.addr.buffer);<br>
> -<br>
> -   /* Flush the sampler cache so any texturing from the destination is<br>
> -    * coherent.<br>
> -    */<br>
> -   brw_emit_mi_flush(brw);<br>
>  }<br>
> --<br>
> 2.5.5<br>
><br>
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<br></blockquote></div><br></div></div></div>