<div dir="ltr">For HiZ, we did this directly in isl_choose_image_alignment_el in isl.c. Maybe it's better to do it there given that they're all 4x4. </div><div class="gmail_extra"> <div class="gmail_quote">On Mon, Jan 16, 2017 at 1:13 AM, Topi Pohjolainen <<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Otherwise i965 driver will start experiencing failures with "texelFetch fs sampler2DMSArray 4 98x1x9-98x129x9 -auto -fbo" on IVB, HSW and BDW when starts to use ISL to calculate the layout. The test is fine on SKL because one already hits: if (isl_format_is_compressed(info->format)) { /* On Gen9, the meaning of RENDER_SURFACE_STATE's * SurfaceHorizontalAlignment and SurfaceVerticalAlignment changed for * compressed formats. They now indicate a multiple of the compression * block. For example, if the compression mode is ETC2 then HALIGN_4 * indicates a horizontal alignment of 16 pixels. * * To avoid wasting memory, choose the smallest alignment possible: * HALIGN_4 and VALIGN_4. */ *image_align_el = isl_extent3d(4, 4, 1); in isl_gen9_choose_image_alignment_el(). However, the same fix is applied on Gen9 for consistency sake. Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>> --- src/intel/isl/isl_gen7.c | 16 ++++++++++++++++ src/intel/isl/isl_gen8.c | 16 ++++++++++++++++ src/intel/isl/isl_gen9.c | 16 ++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c index b1874c1..776d3bf 100644 --- a/src/intel/isl/isl_gen7.c +++ b/src/intel/isl/isl_gen7.c @@ -442,6 +442,22 @@ isl_gen7_choose_image_alignment_el(const struct isl_device *dev, } } + if (fmtl->txc == ISL_TXC_MCS) { + assert(tiling == ISL_TILING_Y0); + + /* + * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": + * + * Height, width, and layout of MCS buffer in this case must match with + * Render Target height, width, and layout. MCS buffer is tiledY. + * + * To avoid wasting memory, choose the smallest alignment possible: + * HALIGN_4 and VALIGN_4. + */ + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + *image_align_el = (struct isl_extent3d) { .w = gen7_choose_halign_el(dev, info), .h = gen7_choose_valign_el(dev, info, tiling), diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c index 81c69dc..c4f8f53 100644 --- a/src/intel/isl/isl_gen8.c +++ b/src/intel/isl/isl_gen8.c @@ -205,6 +205,22 @@ isl_gen8_choose_image_alignment_el(const struct isl_device *dev, return; } + if (fmtl->txc == ISL_TXC_MCS) { + assert(tiling == ISL_TILING_Y0); + + /* + * Broadwell PRM Vol 7, "MCS Buffer for Render Target(s)": + * + * Height, width, and layout of MCS buffer in this case must match with + * Render Target height, width, and layout. MCS buffer is tiledY. + * + * To avoid wasting memory, choose the smallest alignment possible: + * HALIGN_4 and VALIGN_4. + */ + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + /* The below text from the Broadwell PRM provides some insight into the * hardware's requirements for LOD alignment. >From the Broadwell PRM >> * Volume 5: Memory Views >> Surface Layout >> 2D Surfaces: diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c index e5d0f95..8709235 100644 --- a/src/intel/isl/isl_gen9.c +++ b/src/intel/isl/isl_gen9.c @@ -119,6 +119,22 @@ isl_gen9_choose_image_alignment_el(const struct isl_device *dev, return; } + if (fmtl->txc == ISL_TXC_MCS) { + assert(tiling == ISL_TILING_Y0); + + /* + * Skylake PRM Vol 7, "MCS Buffer for Render Target(s)": + * + * Height, width, and layout of MCS buffer in this case must match with + * Render Target height, width, and layout. MCS buffer is tiledY. + * + * To avoid wasting memory, choose the smallest alignment possible: + * HALIGN_4 and VALIGN_4. + */ + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + /* This BSpec text provides some insight into the hardware's alignment * requirements [Skylake BSpec > Memory Views > Common Surface Formats > * Surface Layout and Tiling > 2D Surfaces]: -- 2.5.5 _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div>