<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Mon, Jan 16, 2017 at 1:13 AM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hardware state setup only needs offset and pitch and ignores the<br>
rest.<br></blockquote><div><br></div><div>True... But it seems a a bit sketchy to lie to blorp even if the lie is ok.  This isn't a NAK, just a comment for now.  I need to read further to get more context.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com">topi.pohjolainen@intel.com</a>><br>
---<br>
 src/mesa/drivers/dri/i965/brw_<wbr>blorp.c | 57 ++++++++++++------------------<wbr>-----<br>
 1 file changed, 20 insertions(+), 37 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c b/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c<br>
index ecf27a1..2001cf3 100644<br>
--- a/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c<br>
+++ b/src/mesa/drivers/dri/i965/<wbr>brw_blorp.c<br>
@@ -107,36 +107,6 @@ brw_blorp_init(struct brw_context *brw)<br>
 }<br>
<br>
 static void<br>
-apply_gen6_stencil_hiz_<wbr>offset(struct isl_surf *surf,<br>
-                              struct intel_mipmap_tree *mt,<br>
-                              uint32_t lod,<br>
-                              uint32_t *offset)<br>
-{<br>
-   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);<br>
-<br>
-   if (mt->format == MESA_FORMAT_S_UINT8) {<br>
-      /* Note: we can't compute the stencil offset using<br>
-       * intel_miptree_get_aligned_<wbr>offset(), because the miptree<br>
-       * claims that the region is untiled even though it's W tiled.<br>
-       */<br>
-      *offset = mt->level[lod].level_y * mt->pitch +<br>
-                mt->level[lod].level_x * 64;<br>
-   } else {<br>
-      *offset = intel_miptree_get_aligned_<wbr>offset(mt,<br>
-                                                 mt->level[lod].level_x,<br>
-                                                 mt->level[lod].level_y);<br>
-   }<br>
-<br>
-   surf->logical_level0_px.width = minify(surf->logical_level0_<wbr>px.width, lod);<br>
-   surf->logical_level0_px.height = minify(surf->logical_level0_<wbr>px.height, lod);<br>
-   surf->phys_level0_sa.width = minify(surf->phys_level0_sa.<wbr>width, lod);<br>
-   surf->phys_level0_sa.height = minify(surf->phys_level0_sa.<wbr>height, lod);<br>
-   surf->levels = 1;<br>
-   surf->array_pitch_el_rows =<br>
-      ALIGN(surf->phys_level0_sa.<wbr>height, surf->image_alignment_el.<wbr>height);<br>
-}<br>
-<br>
-static void<br>
 blorp_surf_for_miptree(struct brw_context *brw,<br>
                        struct blorp_surf *surf,<br>
                        struct intel_mipmap_tree *mt,<br>
@@ -181,10 +151,17 @@ blorp_surf_for_miptree(struct brw_context *brw,<br>
        * hacks inside the i965 driver.<br>
        *<br>
        * See also gen6_depth_stencil_state.c<br>
+       *<br>
+       * Note: we can't compute the stencil offset using<br>
+       * intel_miptree_get_aligned_<wbr>offset(), because the miptree<br>
+       * claims that the region is untiled even though it's W tiled.<br>
+       *<br>
+       * In stencil state setup only surf->row_pitch and surf->addr get<br>
+       * consulted. Otherwise surf is ignored and there is no need to adjust<br>
+       * it any further.  See blorp_emit_depth_stencil_<wbr>config().<br>
        */<br>
-      uint32_t offset;<br>
-      apply_gen6_stencil_hiz_offset(<wbr>&tmp_surfs[0], mt, *level, &offset);<br>
-      surf->addr.offset += offset;<br>
+      surf->addr.offset += (mt->level[*level].level_y * mt->pitch +<br>
+                            mt->level[*level].level_x * 64);<br>
       *level = 0;<br>
    }<br>
<br>
@@ -254,11 +231,17 @@ blorp_surf_for_miptree(struct brw_context *brw,<br>
                    hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);<br>
<br>
             /* gen6 requires the HiZ buffer to be manually offset to the<br>
-             * right location.  We could fixup the surf but it doesn't<br>
-             * matter since most of those fields don't matter.<br>
+             * right location.<br>
+             * In depth state setup only surf->aux_surf.row_pitch gets<br>
+             * consulted. Otherwise surf->aux_surf is ignored and there is<br>
+             * no need to adjust it.  See blorp_emit_depth_stencil_<wbr>config().<br>
+             *<br>
+             * surf->aux_surf.row_pitch in turn is set by<br>
+             * intel_miptree_get_aux_isl_<wbr>surf().<br>
              */<br>
-            apply_gen6_stencil_hiz_offset(<wbr>aux_surf, hiz_mt, *level,<br>
-                                          &surf->aux_addr.offset);<br>
+            surf->aux_addr.offset = intel_miptree_get_aligned_<wbr>offset(hiz_mt,<br>
+                                       hiz_mt->level[*level].level_x,<br>
+                                       hiz_mt->level[*level].level_y)<wbr>;<br>
             assert(hiz_mt->pitch == aux_surf->row_pitch);<br>
          }<br>
       }<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.5.5<br>
<br>
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</font></span></blockquote></div><br></div></div>