<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Mon, Jan 16, 2017 at 1:13 AM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">This series is a step towards using ISL instead of current<br>
intel_mipnap_tree/brw_tex_<wbr>layout logic in i965. First 11 patches<br>
simplify the workspace for the rest and more functional changes.<br>
<br>
Next seven patches introduce simple on-demand calculators for<br>
stencil and hiz offsets on gen6. On gen6 hardware doesn't support<br>
mipmaps for stencil or hiz. Driver works around this by offsetting<br>
hiz/stencil surfaces to desired level-of-detail. Current logic<br>
relies on pre-computed offset table which is replaced by helpers<br>
functions calculating the offsets when needed. This drops dependency<br>
to intel_mipnap_tree.<br>
<br>
Patch 22 prepares ISL to provide large enough auxiliary size for<br>
MCS on gen7 and on gen8. I started seeing intermittent failures (once<br>
in 10 subsequent runs) with<br>
"texelFetch fs sampler2DMSArray 4 98x1x9-98x129x9 -auto -fbo" with<br>
IVB, HSW and BDW, but not with SKL. After some debugging I tracked<br>
this down to SKL using vertical alignment of four requiring 4608<br>
bytes (and driver allocated two pages). Earlier gens used vertical<br>
alignment of one and only allocated one page. More details in the<br>
patch.<br>
I included patch 21 for consistency sake as to me it seems we are<br>
missing something of that sort.<br>
<br>
Patch 23 starts using ISL for MCS and the rest for HIZ.<br>
<br>
<br>
I tried to make individual steps as small as possible adding<br>
temporary asserts checking that newly added calculations matched<br>
the current.<br>
<br>
Topi Pohjolainen (27):<br>
i965/meta: Remove unused brw_get_rb_for_slice()<br>
i965/miptree: Remove redundant check for null texture<br>
i965: Remove check for hiz on earlier gens than SNB<br>
i965/gen6: Remove check for stencil format<br>
i965: Replace open coded with intel_miptree_get_image_<wbr>offset()<br>
i965/blorp/gen6: Simplify hiz surface setup<br>
i965/gen6: Simplify hiz surface setup<br>
i965/blorp/gen6: Remove dead code in hiz setup<br>
i965/gen6: Remove dead code in hiz surface setup<br>
i965/blorp/gen6: Drop unnecessary stencil/hiz surf dimension adjust<br>
i965/hiz/gen6: Stop setting false qpitch<br></blockquote><div><br><div><div><div><div>I believe I already gave you reviews on everything through 11 (though there was one patch we agreed would be dropped).<br></div></div></div></div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
i965/gen6: Calculate stencil offset on demand<br>
i965/gen6: Calculate hiz offset on demand<br></blockquote><div><br>So
long as you promise to eventually try and come up with something better than
all_slices_at_each_lod and delete the nasty code once and for all, 12
and 13 are<br><div><br></div>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br><br></div><div>Feel fre to wait to make that change (not using all_sices_at_each_lod) until after the rest of the ISL churn is done and we have a better idea of what the bright new future of ISL-based GL looks like.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
i965/blorp/gen6: Use on-demand stencil/hiz offset resolvers<br>
i965/gen6: Drop miptrees in depth/stencil offset resolvers<br>
i965/blorp/gen6: Set aux pitch directly<br>
i965/gen6/hiz: Add direct buffer size resolver<br>
i965/gen6: Allocate hiz directly without miptree<br>
i965/miptree: Refactor aux surface allocation<br>
i965/miptree: Refactor ISL aux usage resolver<br></blockquote><div><br>14-20 are<br><br>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
intel/isl/gen7: Add CCS alignment restrictions<br></blockquote><div><br></div><div>I'm fairly sure that patch 21 is bogus<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
intel/isl: Apply render target alignment constraints for MCS<br></blockquote><div><br></div><div>I asked for a change on 22<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
i965/miptree: Use ISL for MCS layouts<br>
i965/miptree: Drop MIPTREE_LAYOUT_ACCELERATED_<wbr>UPLOAD in mcs init<br>
i965/miptree/gen7+: Use ISL for HIZ layouts<br>
i965/blorp: Use hiz surface instead of creating copy<br>
i965: Use stored hiz surface instead of creating copy<br></blockquote><div><br></div><div>23-27 are<br><br>Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>><br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
src/intel/isl/isl_gen7.c | 55 +++<br>
src/intel/isl/isl_gen8.c | 16 +<br>
src/intel/isl/isl_gen9.c | 16 +<br>
src/mesa/drivers/dri/i965/brw_<wbr>blorp.c | 108 ++---<br>
src/mesa/drivers/dri/i965/brw_<wbr>context.h | 6 -<br>
src/mesa/drivers/dri/i965/brw_<wbr>meta_util.c | 44 --<br>
src/mesa/drivers/dri/i965/brw_<wbr>meta_util.h | 5 -<br>
src/mesa/drivers/dri/i965/brw_<wbr>misc_state.c | 23 +-<br>
src/mesa/drivers/dri/i965/brw_<wbr>tex_layout.c | 131 ++++++<br>
src/mesa/drivers/dri/i965/brw_<wbr>wm_surface_state.c | 13 +-<br>
src/mesa/drivers/dri/i965/<wbr>gen6_depth_state.c | 45 +-<br>
src/mesa/drivers/dri/i965/<wbr>gen7_misc_state.c | 5 +-<br>
src/mesa/drivers/dri/i965/<wbr>gen8_depth_state.c | 6 +-<br>
src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.c | 548 ++++++-----------------<br>
src/mesa/drivers/dri/i965/<wbr>intel_mipmap_tree.h | 45 +-<br>
src/mesa/drivers/dri/i965/<wbr>intel_pixel_read.c | 16 +-<br>
16 files changed, 472 insertions(+), 610 deletions(-)<br>
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