<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Tue, Jan 31, 2017 at 4:44 PM, Jason Ekstrand <span dir="ltr"><<a href="mailto:jason@jlekstrand.net" target="_blank">jason@jlekstrand.net</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><div><div class="h5">On Mon, Jan 16, 2017 at 1:13 AM, Topi Pohjolainen <span dir="ltr"><<a href="mailto:topi.pohjolainen@gmail.com" target="_blank">topi.pohjolainen@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">This is kept on purpose in i965. It can be moved to ISL if it<br>
is needed in vulkan.<br>
<br>
Pointers to miptrees are given solely for verification purposes.<br>
These will be dropped in following patches.<br>
<br>
Signed-off-by: Topi Pohjolainen <<a href="mailto:topi.pohjolainen@intel.com" target="_blank">topi.pohjolainen@intel.com</a>><br>
---<br>
src/mesa/drivers/dri/i965/<wbr>brw_tex_layout.c | 44 +++++++++++++++++++++++++++<br>
src/mesa/drivers/dri/i965/gen<wbr>6_depth_state.c | 18 ++++++++---<br>
src/mesa/drivers/dri/i965/int<wbr>el_mipmap_tree.h | 11 +++++++<br>
3 files changed, 69 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/src/mesa/drivers/dri/i965/br<wbr>w_tex_layout.c b/src/mesa/drivers/dri/i965/br<wbr>w_tex_layout.c<br>
index 80b341a..6f1c228 100644<br>
--- a/src/mesa/drivers/dri/i965/br<wbr>w_tex_layout.c<br>
+++ b/src/mesa/drivers/dri/i965/br<wbr>w_tex_layout.c<br>
@@ -353,6 +353,50 @@ brw_stencil_all_slices_at_each<wbr>_lod_offset(const struct isl_surf *surf,<br>
return level_y * two_rows_interleaved_pitch + level_x * 64;<br>
}<br>
<br>
+uint32_t<br>
+brw_get_mipmap_total_width(un<wbr>signed w0, unsigned num_levels, unsigned halign)<br>
+{<br>
+ /* If there is not level two, no adjustment is needed. */<br>
+ if (num_levels < 2)<br>
+ return ALIGN(w0, halign);<br>
+<br>
+ const uint32_t w1 = ALIGN(minify(w0, 1), halign);<br>
+ const uint32_t w2 = minify(w0, 2);<br>
+<br>
+ /* Levels one and two sit side-by-side below level zero. Due to alignment<br>
+ * of level one levels one and two may require more space than level zero.<br>
+ */<br>
+ return ALIGN(MAX2(w0, w1 + w2), halign);<br>
+}<br>
+<br>
+uint32_t<br>
+brw_hiz_all_slices_at_each_lo<wbr>d_offset(<br>
+ const struct isl_extent4d *phys_level0_sa,<br>
+ enum isl_surf_dim dim, unsigned num_levels,<br>
+ enum isl_format format,<br>
+ const struct intel_mipmap_tree *mt,<br>
+ unsigned level)<br>
+{<br>
+ assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);<br>
+<br>
+ const uint32_t cpp = isl_format_get_layout(format)-<wbr>>bpb / 8;<br>
+ const uint32_t halign = 128 / cpp;<br>
+ const uint32_t valign = 32;<br></blockquote><div><br></div></div></div><div>I'm very sure that this calculation (using the cpp of the depth format) is completely bogus. However, given the asserts below, I would also easily believe that it's exactly the same calculation as we've always done so let's leave it for now.<br></div><div><div class="h5"><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+ const uint32_t level_x = all_slices_at_each_lod_x_offse<wbr>t(<br>
+ phys_level0_sa->width, halign, level);<br>
+ const uint32_t level_y = all_slices_at_each_lod_y_offse<wbr>t(<br>
+ phys_level0_sa, dim, valign, level);<br>
+ const uint32_t pitch = brw_get_mipmap_total_width(<br>
+ phys_level0_sa->width, num_levels, halign) * cpp;<br>
+<br>
+ assert(level_x == mt->level[level].level_x);<br>
+ assert(level_y == mt->level[level].level_y);<br>
+ assert(pitch == mt->pitch);<br>
+ assert(cpp == mt->cpp);<br>
+<br>
+ return level_y * pitch + level_x / halign * 4096;<br>
+}<br>
+<br>
static void<br>
brw_miptree_layout_2d(struct intel_mipmap_tree *mt)<br>
{<br>
diff --git a/src/mesa/drivers/dri/i965/ge<wbr>n6_depth_state.c b/src/mesa/drivers/dri/i965/ge<wbr>n6_depth_state.c<br>
index 80cb890..05565de 100644<br>
--- a/src/mesa/drivers/dri/i965/ge<wbr>n6_depth_state.c<br>
+++ b/src/mesa/drivers/dri/i965/ge<wbr>n6_depth_state.c<br>
@@ -165,10 +165,20 @@ gen6_emit_depth_stencil_hiz(st<wbr>ruct brw_context *brw,<br>
<br>
assert(hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);<br>
<br>
- const uint32_t offset = intel_miptree_get_aligned_offs<wbr>et(<br>
- hiz_mt,<br>
- hiz_mt->level[lod].level_x,<br>
- hiz_mt->level[lod].level_y);<br>
+ struct isl_surf temp_surf;<br>
+ intel_miptree_get_isl_surf(br<wbr>w, mt, &temp_surf);<br>
+<br>
+ /* Main and hiz surfaces agree on the base level dimensions and<br>
+ * format. Therefore one can calculate against the main surface.<br></blockquote></div></div></div></div></div></blockquote><div><br></div><div>Also, on the list of things that I can totally believe are true but shouldn't be, this comment is one of them. :-(<br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><div><div class="h5"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+ */<br>
+ const uint32_t offset = brw_hiz_all_slices_at_each_lod<wbr>_offset(<br>
+ &temp_surf.phys_level0_sa, temp_surf.dim, temp_surf.levels,<br>
+ temp_surf.format, hiz_mt, lod);<br>
+<br>
+ assert(offset == intel_miptree_get_aligned_offs<wbr>et(<br>
+ hiz_mt,<br>
+ hiz_mt->level[lod].level_x,<br>
+ hiz_mt->level[lod].level_y));<br>
<br>
BEGIN_BATCH(3);<br>
OUT_BATCH((_3DSTATE_HIER_DEPT<wbr>H_BUFFER << 16) | (3 - 2));<br>
diff --git a/src/mesa/drivers/dri/i965/in<wbr>tel_mipmap_tree.h b/src/mesa/drivers/dri/i965/in<wbr>tel_mipmap_tree.h<br>
index e51872f..11c61c2 100644<br>
--- a/src/mesa/drivers/dri/i965/in<wbr>tel_mipmap_tree.h<br>
+++ b/src/mesa/drivers/dri/i965/in<wbr>tel_mipmap_tree.h<br>
@@ -984,10 +984,21 @@ brw_miptree_get_vertical_slice<wbr>_pitch(const struct brw_context *brw,<br>
unsigned level);<br>
<br>
uint32_t<br>
+brw_get_mipmap_total_width(un<wbr>signed w0, unsigned num_levels, unsigned halign);<br>
+<br>
+uint32_t<br>
brw_stencil_all_slices_at_eac<wbr>h_lod_offset(const struct isl_surf *surf,<br>
const struct intel_mipmap_tree *mt,<br>
uint32_t level);<br>
<br>
+uint32_t<br>
+brw_hiz_all_slices_at_each_lo<wbr>d_offset(<br>
+ const struct isl_extent4d *phys_level0_sa,<br>
+ enum isl_surf_dim dim, unsigned num_levels,<br>
+ enum isl_format format,<br>
+ const struct intel_mipmap_tree *mt,<br>
+ unsigned level);<br>
+<br>
void<br>
brw_miptree_layout(struct brw_context *brw,<br>
struct intel_mipmap_tree *mt,<br>
<span class="m_4659904470836470008HOEnZb"><font color="#888888">--<br>
2.5.5<br>
<br>
______________________________<wbr>_________________<br>
mesa-dev mailing list<br>
<a href="mailto:mesa-dev@lists.freedesktop.org" target="_blank">mesa-dev@lists.freedesktop.org</a><br>
<a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/<wbr>mailman/listinfo/mesa-dev</a><br>
</font></span></blockquote></div></div></div><br></div></div>
</blockquote></div><br></div></div>